Peripheral operating requirements and behaviors
Table 22. EzPort switching specifications (continued)
Num
EP1
EP1a
EP2
EP3
EP4
EP5
EP6
EP7
EP8
EP9
Description
EZP_CK frequency of operation (all commands except
READ)
EZP_CK frequency of operation (READ command)
EZP_CS negation to next EZP_CS assertion
EZP_CS input valid to EZP_CK high (setup)
EZP_CK high to EZP_CS input invalid (hold)
EZP_D input valid to EZP_CK high (setup)
EZP_CK high to EZP_D input invalid (hold)
EZP_CK low to EZP_Q output valid
EZP_CK low to EZP_Q output invalid (hold)
EZP_CS negation to EZP_Q tri-state
Min.
—
—
2 x t
EZP_CK
5
5
2
5
—
0
—
Max.
f
SYS
/2
f
SYS
/8
—
—
—
—
—
17
—
12
Unit
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
EZP_CK
EP3
EP4
EP2
EZP_CS
EP8
EP9
EP7
EZP_Q (output)
EP5
EP6
EZP_D (input)
Figure 9. EzPort Timing Diagram
6.5 Security and integrity modules
There are no specifications necessary for the device's security and integrity modules.
6.6 Analog
K10 Sub-Family Data Sheet, Rev. 4 5/2012.
Freescale Semiconductor, Inc.
35
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
