Pinout
Table 20. Clock Configurations for PCI Agent Mode (PCI_MODCK=1)
1,2
(continued)
Mode
3
MODCK_H-
MODCK[1-3]
1110_000
1110_001
1110_010
1110_011
PCI Clock
(MHz)
Low
25.0
25.0
28.6
25.0
High
50.0
50.0
50.0
50.0
CPM Clock
(MHz)
Low
High
CPU Clock
(MHz)
Low
High
Bus Clock
(MHz)
Low
High
CPM
Multiplication
Factor
4
CPU
Multiplication
Factor
5
Bus
Division
Factor
5
5
5
5
125.0 250.0
125.0 250.0
142.9 250.0
125.0 250.0
2.5
3
3.5
4
156.3 312.5
187.5 375.0
250.0 437.5
250.0 500.0
2
2
2
2
62.5 125.0
62.5 125.0
71.4 125.0
62.5 125.0
1110_100
1110_101
1110_110
1110_111
25.0
25.0
25.0
25.0
50.0
50.0
50.0
50.0
5
5
5
5
125.0 250.0
125.0 250.0
125.0 250.0
125.0 250.0
4
4.5
5
5.5
166.7 333.3
187.5 375.0
208.3 416.7
229.2 458.3
3
3
3
3
41.7
41.7
41.7
41.7
83.3
83.3
83.3
83.3
1100_000
1100_001
1100_010
1
Reserved
Reserved
Reserved
2
3
4
5
The “low” values are the minimum allowable frequencies for a given clock mode. The minimum bus frequency in a
table entry guarantees only the required minimum CPU operating frequency. The “high” values are for the purpose of
illustration only. Users must select a mode and input bus frequency so that the resulting configuration does not exceed
the frequency rating of the user’s device. The minimum CPU frequency is 150 MHz for commercial temperature
devices and 175 MHz for extended temperature devices. The minimum CPM frequency is 120 MHz.
PCI_MODCK determines the PCI clock frequency range. See
for higher range configurations.
MODCK_H = hard reset configuration word [28–31] (see Section 5.4 in the SoC reference manual). MODCK[1-3] =
three hardware configuration pins.
CPM multiplication factor = CPM clock/bus clock
CPU multiplication factor = Core PLL multiplication factor
8
Pinout
This figure and table show the pin assignments and pinout for the 516 PBGA package.
MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3
Freescale Semiconductor
43
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
