System Design Information
21 System Design Information
This section provides electrical and thermal design recommendations for successful application of the
MPC8347EA.
21.1 System Clocking
The MPC8347EA includes two PLLs:
1. The platform PLL generates the platform clock from the externally supplied CLKIN input. The
frequency ratio between the platform and CLKIN is selected using the platform PLL ratio
configuration bits as described in Section 19.1, “System PLL Configuration.”
2. The e300 core PLL generates the core clock as a slave to the platform clock. The frequency ratio
between the e300 core clock and the platform clock is selected using the e300 PLL ratio
configuration bits as described in Section 19.2, “Core PLL Configuration.”
21.2 PLL Power Supply Filtering
Each PLL gets power through independent power supply pins (AV 1, AV 2, respectively). The AV
DD
DD
DD
level should always equal to V , and preferably these voltages are derived directly from V through a
DD
DD
low frequency filter scheme.
There are a number of ways to provide power reliably to the PLLs, but the recommended solution is to
provide four independent filter circuits as illustrated in Figure 43, one to each of the four AV pins.
DD
Independent filters to each PLL reduce the opportunity to cause noise injection from one PLL to the other.
The circuit filters noise in the PLL resonant frequency range from 500 kHz to 10 MHz. It should be built
with surface mount capacitors with minimum effective series inductance (ESL). Consistent with the
recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook of Black Magic
(Prentice Hall, 1993), multiple small capacitors of equal value are recommended over a single large value
capacitor.
To minimize noise coupled from nearby circuits, each circuit should be placed as closely as possible to the
specific AV pin being supplied. It should be possible to route directly from the capacitors to the AV
DD
DD
pin, which is on the periphery of package, without the inductance of vias.
Figure 43 shows the PLL power supply filter circuit.
10 Ω
VDD
AVDD (or L2AVDD)
2.2 µF
2.2 µF
Low ESL Surface Mount Capacitors
GND
Figure 43. PLL Power Supply Filter Circuit
21.3 Decoupling Recommendations
Due to large address and data buses and high operating frequencies, the MPC8347EA can generate
transient power surges and high frequency noise in its power supply, especially while driving large
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12
Freescale Semiconductor
91
FREESCALE [ Freescale ]
