I2C
2
Table 43. I C AC Electrical Specifications (continued)
Parameter
Symbol1
Min
Max
Unit
__
Fall time of both SDA and SCL signals5
Setup time for STOP condition
tI2CF
tI2PVKH
tI2KHDX
VNL
300
—
ns
μs
μs
V
0.6
1.3
Bus free time between a STOP and START condition
—
Noise margin at the LOW level for each connected device (including
hysteresis)
0.1 × OVDD
—
Noise margin at the HIGH level for each connected device (including
hysteresis)
VNH
0.2 × OVDD
—
V
Notes:
1. The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs
and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tI2DVKH symbolizes I2C timing (I2) with
respect to the time data input signals (D) reach the valid state (V) relative to the tI2C clock reference (K) going to the high (H)
state or setup time. Also, tI2SXKL symbolizes I2C timing (I2) for the time that the data with respect to the start condition (S)
goes invalid (X) relative to the tI2C clock reference (K) going to the low (L) state or hold time. Also, tI2PVKH symbolizes I2C
timing (I2) for the time that the data with respect to the stop condition (P) reaches the valid state (V) relative to the tI2C clock
reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention is used with the appropriate
letter: R (rise) or F (fall).
2. The device provides a hold time of at least 300 ns for the SDA signal (referred to the VIH(min) of the SCL signal) to bridge
the undefined region of the falling edge of SCL.
3. The maximum tI2DVKH must be met only if the device does not stretch the LOW period (tI2CL) of the SCL signal.
4. CB = capacitance of one bus line in pF.
5.)The device does not follow the “I2C-BUS Specifications” version 2.1 regarding the tI2CF AC parameter.
2
Figure 32 provides the AC test load for the I C.
OVDD/2
Output
Z0 = 50 Ω
RL = 50 Ω
2
Figure 32. I C AC Test Load
2
Figure 33 shows the AC timing diagram for the I C bus.
SDA
tI2CF
tI2CL
tI2DVKH
tI2KHKL
tI2CF
tI2SXKL
tI2CR
SCL
tI2SXKL
tI2CH
tI2SVKH
tI2PVKH
tI2DXKL
S
Sr
Figure 33. I C Bus AC Timing Diagram
P
S
2
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12
Freescale Semiconductor
47
FREESCALE [ Freescale ]
