System Design Information
OV
DD
SRESET
HRESET
10 kΩ
SRESET
6
HRESET
1
From Target
Board Sources
(if any)
10 kΩ
13
11
COP_HRESET
COP_SRESET
10 kΩ
10 kΩ
5
10 kΩ
10 kΩ
TRST
1
1
3
5
7
9
11
2
4
6
8
10
12
4
6
5
COP Header
15
14
3
COP_TRST
COP_VDD_SENSE
2
NC
COP_CHKSTP_OUT
10 kΩ
10 kΩ
COP_CHKSTP_IN
10
Ω
CKSTP_OUT
KEY
13
No pin
8
COP_TMS
9
COP_TDO
COP_TDI
COP_TCK
7
2
10
12
16
NC
NC
4
CKSTP_IN
TMS
TDO
TDI
TCK
10 kΩ
15
16
COP Connector
Physical Pinout
1
3
Notes:
1. The COP port and target board should be able to independently assert HRESET and TRST to the processor
in order to fully control the processor as shown here.
2. Populate this with a 10
Ω
resistor for short-circuit/current-limiting protection.
3. The KEY location (pin 14) is not physically present on the COP header.
4. Although pin 12 is defined as a No-Connect, some debug tools may use pin 12 as an additional GND pin for
improved signal integrity.
5. This switch is included as a precaution for BSDL testing. The switch should be open during BSDL testing to avoid
accidentally asserting the TRST line. If BSDL testing is not being performed, this switch should be closed or removed.
6. Asserting SRESET causes a machine check interrupt to the e500 core.
Figure 52. JTAG Interface Connection
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
83
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
