JTAG
Table 52. JTAG AC Timing Specifications (Independent of SYSCLK)
1
(continued)
At recommended operating conditions with OV
DD
of 3.3 V ± 5%.
Parameter
JTAG external clock to output high impedance:
Boundary-scan data
TDO
Symbol
2
Min
Max
Unit
ns
Notes
t
JTKLDZ
t
JTKLOZ
3
3
19
9
5, 6
Notes:
1. All outputs are measured from the midpoint voltage of the falling/rising edge of t
TCLK
to the midpoint of the signal in question.
The output timings are measured at the pins. All output timings assume a purely resistive 50-Ω load (see
Figure 36).
Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.
2. The symbols used for timing specifications herein follow the pattern of t
(first two letters of functional block)(signal)(state) (reference)(state)
for inputs and t
(first two letters of functional block)(reference)(state)(signal)(state)
for outputs. For example, t
JTDVKH
symbolizes JTAG
device timing (JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the t
JTG
clock reference
(K) going to the high (H) state or setup time. Also, t
JTDXKH
symbolizes JTAG timing (JT) with respect to the time data input
signals (D) went invalid (X) relative to the t
JTG
clock reference (K) going to the high (H) state. Note that, in general, the clock
reference symbol representation is based on three letters representing the clock of a particular functional. For rise and fall
times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
3. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.
4. Non-JTAG signal input timing with respect to t
TCLK
.
5. Non-JTAG signal output timing with respect to t
TCLK
.
6. Guaranteed by design.
Figure 36
provides the AC test load for TDO and the boundary-scan outputs.
Output
Z
0
= 50
Ω
R
L
= 50
Ω
OV
DD
/2
Figure 36. AC Test Load for the JTAG Interface
Figure 37
provides the JTAG clock input timing diagram.
JTAG
External Clock
VM
t
JTKHKL
t
JTG
VM = Midpoint Voltage (OVDD/2)
VM
VM
t
JTGR
t
JTGF
Figure 37. JTAG Clock Input Timing Diagram
Figure 38
provides the TRST timing diagram.
TRST
VM
t
TRST
VM = Midpoint Voltage (OVDD/2)
VM
Figure 38. TRST Timing Diagram
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4
66
Freescale Semiconductor
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
