Overview
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Auto-detection of 1x- and 4x-mode operation during port initialization
Link initialization and synchronization
Large and small size transport information field support selectable at initialization time
34-bit addressing
Up to 256 bytes data payload
All transaction flows and priorities
Atomic set/clr/inc/dec for read-modify-write operations
Generation of IO_READ_HOME and FLUSH with data for accessing cache-coherent data at
a remote memory system
— Receiver-controlled flow control
— Error detection, recovery, and time-out for packets and control symbols as required by the
RapidIO specification
— Register and register bit extensions as described in part VIII (Error Management) of the
RapidIO specification
— Hardware recovery only
— Register support is not required for software-mediated error recovery.
— Accept-all mode of operation for fail-over support
— Support for RapidIO error injection
— Internal LP-serial and application interface-level loopback modes
— Memory and PHY BIST for at-speed production test
RapidIO–compliant message unit
— 4 Kbytes of payload per message
— Up to sixteen 256-byte segments per message
— Two inbound data message structures within the inbox
— Capable of receiving three letters at any mailbox
— Two outbound data message structures within the outbox
— Capable of sending three letters simultaneously
— Single segment multicast to up to 32 devIDs
— Chaining and direct modes in the outbox
— Single inbound doorbell message structure
— Facility to accept port-write messages
Three PCI Express controllers
— PCI Express 1.0a compatible
— Supports x8, x4, x2, and x1 link widths (see following bullet for specific width configuration
options)
— Auto-detection of number of connected lanes
— Selectable operation as root complex or endpoint
— Both 32- and 64-bit addressing
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4
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Freescale Semiconductor
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
