Freescale Semiconductor
Technical Data
Document Number: MPC8572EEC
Rev. 4, 06/2010
MPC8572E PowerQUICC III
Integrated Processor
Hardware Specifications
1
Overview
Contents
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . 10
2
This section provides a high-level overview of the features
of the MPC8572E processor.
Figure 1
shows the major
functional units within the MPC8572E.
1.1
Key Features
1.
2.
The following list provides an overview of the MPC8572E
feature set:
• Two high-performance 32-bit Book E–enhanced
cores that implement the Power Architecture
®
technology:
— Each core is identical to the core within the
MPC8548 processor.
— 32-Kbyte L1 instruction cache and 32-Kbyte L1
data cache with parity protection. Caches can be
locked entirely or on a per-line basis, with
separate locking for instructions and data.
— Signal-processing engine (SPE) APU (auxiliary
processing unit). Provides an extensive
instruction set for vector (64-bit) integer and
fractional operations. These instructions use both
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