DDR2 and DDR3 SDRAM Controller
Table 17. DDR2 and DDR3 SDRAM Interface Output AC Timing Specifications (continued)
At recommended operating conditions with GVDD of 1.8 V ± 5% for DDR2 or 1.5 V ± 5% for DDR3.
1
Parameter
Symbol
Min
Max
Unit
Notes
400 MHz
t
t
1.95
—
ns
ns
3
3
DDKHCS
MCS[n] output hold with respect to MCK
DDKHCX
800 MHz
0.917
1.10
1.48
1.95
—
—
—
—
667 MHz
533 MHz
400 MHz
MCK to MDQS Skew
800 MHz
t
ns
ps
4
5
DDKHMH
–0.375
–0.6
0.375
0.6
<= 667 MHz
MDQ/MECC/MDM output setup with respect
to MDQS
t
DDKHDS,
t
DDKLDS
800 MHz
667 MHz
533 MHz
400 MHz
375
450
538
700
—
—
—
—
MDQ/MECC/MDM output hold with respect to
MDQS
t
t
ps
5
DDKHDX,
DDKLDX
800 MHz
375
450
538
700
—
—
—
—
667 MHz
533 MHz
400 MHz
MDQS preamble start
800 MHz
t
t
ns
ns
6
6
DDKHMP
DDKHME
–0.5 × t
–
–0.5 × t
MCK
0.375
MCK
+0.375
– 0.6 –0.5 × t +0.6
MCK
<= 667 MHz
–0.5 × t
MCK
MDQS epilogue end
800 MHz
–0.375
0.375
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
23
FREESCALE [ Freescale ]
