Ethernet: Enhanced Three-Speed Ethernet (eTSEC)
t
FIRR
t
FIR
RX_CLK
t
FIRH
t
FIRF
RXD[7:0]
RX_DV
RX_ER
valid data
t
t
FIRDV
FIRDX
Figure 8. FIFO Receive AC Timing Diagram
8.2.2
GMII AC Timing Specifications
This section describes the GMII transmit and receive AC timing specifications.
8.2.2.1
GMII Transmit AC Timing Specifications
Table 26 provides the GMII transmit AC timing specifications.
Table 26. GMII Transmit AC Timing Specifications
At recommended operating conditions with LVDD/TVDD of 2.5/ 3.3 V ± 5%.
1
Parameter/Condition
Symbol
Min
Typ
Max
Unit
GMII data TXD[7:0], TX_ER, TX_EN setup time
GTX_CLK to GMII data TXD[7:0], TX_ER, TX_EN delay
GTX_CLK data clock rise time (20%-80%)
GTX_CLK data clock fall time (80%-20%)
Notes:
t
2.5
0.5
—
—
—
—
—
—
ns
ns
ns
ns
GTKHDV
t
5.0
1.0
1.0
GTKHDX
2
t
GTXR
2
t
—
GTXF
1. The symbols used for timing specifications herein follow the pattern t
(first two letters of functional block)(signal)(state) (reference)(state)
for inputs and t
for outputs. For example, t
symbolizes GMII
(first two letters of functional block)(reference)(state)(signal)(state)
GTKHDV
transmit timing (GT) with respect to the t
clock reference (K) going to the high state (H) relative to the time date input
GTX
signals (D) reaching the valid state (V) to state or setup time. Also, t
symbolizes GMII transmit timing (GT) with respect
GTKHDX
to the t
clock reference (K) going to the high state (H) relative to the time date input signals (D) going invalid (X) or hold
GTX
time. Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a
particular functional. For example, the subscript of t represents the GMII(G) transmit (TX) clock. For rise and fall times,
GTX
the latter convention is used with the appropriate letter: R (rise) or F (fall).
2. Guaranteed by design.
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
32
FREESCALE [ Freescale ]
