Freescale Semiconductor
Technical Data
Document Number: MPC8544EEC
Rev. 3, 11/2009
MPC8544E PowerQUICC™ III
Integrated Processor
Hardware Specifications
1
MPC8544E Overview
Contents
This section provides a high-level overview of MPC8544E
features.
shows the major functional units within
the device.
1.1
Key Features
The following list provides an overview of the device feature
set:
• High-performance 32-bit Book E–enhanced core
built on Power Architecture™ technology:
— 32-Kbyte L1 instruction cache and 32-Kbyte L1
data cache with parity protection. Caches can be
locked entirely or on a per-line basis, with
separate locking for instructions and data.
— Signal-processing engine (SPE) APU (auxiliary
processing unit). Provides an extensive
instruction set for vector (64-bit) integer and
fractional operations. These instructions use both
the upper and lower words of the 64-bit GPRs as
they are defined by the SPE APU.
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