Freescale Semiconductor
Data Sheet: Technical Data
Document Number: MPC5125
Rev. 3, 11/2009
MPC5125
MPC5125 Microcontroller
Data Sheet
The MPC5125 integrates a high performance e300 CPU core
based on the Power Architecture™ Technology with a rich set
of peripheral functions focused on communications and
systems integration.
Major features of the MPC5125 are as follows:
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e300 Power Architecture processor core (enhanced
version of the MPC603e core), operates as fast as
400 MHz
Low power design
Display interface unit (DIU)
DDR1, DDR2, low-power mobile DDR (LPDDR),
and 1.8 V/3.3 V SDR DRAM memory controllers
32 KB on-chip SRAM
USB 2.0 OTG controller with ULPI interface
DMA subsystem
Flexible multi-function external memory bus (EMB)
interface
NAND flash controller (NFC)
LocalPlus interface (LPC)
10/100Base Ethernet
MMC/SD/SDIO card host controller (SDHC)
Programmable serial controller (PSC)
Inter-integrated circuit (I
2
C) communication
interfaces
Controller area network (CAN)
J1850 byte data link controller (BDLC) interface
On-chip real-time clock (RTC)
On-chip temperature sensor
IC Identification module (IIM)
324 TEPBGA
23 mm x 23 mm
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This document contains information on a product under development. Freescale reserves the
right to change or discontinue this product without notice.
© Freescale Semiconductor, Inc., 2008–2009. All rights reserved.
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