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FT232BL 参数 Datasheet PDF下载

FT232BL图片预览
型号: FT232BL
PDF下载: 下载PDF文件 查看货源
内容描述: USB UART ( USB - 串行) I.C. [USB UART ( USB - Serial) I.C.]
分类和应用: 外围集成电路PC时钟
文件页数/大小: 26 页 / 560 K
品牌: FTDI [ FUTURE TECHNOLOGY DEVICES INTERNATIONAL LTD. ]
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FT232BQ USB UART ( USB - Serial) I.C.  
POWER CONTROL GROUP  
Pin#  
10  
Signal  
Type  
Description  
SLEEP#  
OUT  
Goes Low during USB Suspend Mode. Typically used to power-down an external  
TTL to RS232 level converter i.c. in USB <=> RS232 converter designs.  
15  
PWREN#  
PWRCTL  
OUT  
IN  
Goes Low after the device is configured via USB, then high during USB suspend.  
Can be used to control power to external logic using a P-Channel Logic Level  
MOSFET switch. Enable the Interface Pull-Down Option in EEPROM when using  
the PWREN# pin in this way.  
14  
Bus Powered – Tie Low / Self Powered – Tie High (to VCCIO)  
MISCELLANEOUS SIGNAL GROUP  
Pin#  
4
Signal  
Type  
Description  
RESET#  
IN  
Can be used by an external device to reset the FT232BQ. If not required, tie to  
VCC.  
5
RSTOUT#  
OUT  
Output of the internal Reset Generator. Stays high impedance for ~ 5ms after  
VCC > 3.5V and the internal clock starts up, then clamps its output to the 3.3v  
output of the internal regulator. Taking RESET# low will also force RSTOUT# to  
drive low. RSTOUT# is NOT affected by a USB Bus Reset.  
12  
11  
27  
TXLED#  
RXLED#  
XTIN  
O.C.  
O.C.  
IN  
LED Drive - Pulses Low when Transmitting Data via USB  
LED Drive - Pulses Low when Receiving Data via USB  
Input to 6MHz Crystal Oscillator Cell. This pin can also be driven by an external  
6MHz clock if required. Note : Switching threshold of this pin is VCC/2, so if  
driving from an external source, the source must be driving at 5V CMOS level or  
a.c. coupled to centre around VCC/2.  
28  
31  
XTOUT  
TEST  
OUT  
IN  
Output from 6MHz Crystal Oscillator Cell. XTOUT stops oscillating during USB  
suspend, so take care if using this signal to clock external logic.  
Puts device in I.C. test mode – must be tied to GND for normal operation.  
POWER AND GND GROUP  
Pin#  
6
Signal  
Type  
Description  
3V3OUT  
OUT  
3.3 volt Output from the integrated L.D.O. regulator This pin should be decoupled  
to GND using a 33nF ceramic capacitor in close proximity to the device pin. Its  
prime purpose is to provide the internal 3.3V supply to the USB transceiver cell  
and the RSTOUT# pin. A small amount of current (<= 5mA) can be drawn from  
this pin to power external 3.3v logic if required.  
3,26  
13  
VCC  
PWR  
PWR  
+4.35 volt to +5.25 volt VCC to the device core, LDO and non-UART interface  
pins.  
VCCIO  
+3.0 volt to +5.25 volt VCC to the UART interface pins 10..12, 14..16 and 18..25.  
When interfacing with 3.3V external logic in a bus powered design connect  
VCCIO to a 3.3V supply generated from the USB bus. When interfacing with  
3.3V external logic in a self powered design connect VCCIO to the 3.3V supply  
of the external logic. Otherwise connect to VCC to drive out at 5V CMOS level.  
9,17  
30  
GND  
PWR  
PWR  
PWR  
Device - Ground Supply Pins  
AVCC  
AGND  
Device - Analog Power Supply for the internal x8 clock multiplier  
Device - Analog Ground Supply for the internal x8 clock multiplier  
29  
**Note 1 - During device reset, these pins are tri-state but pulled up to VCC via internal 200K resistors.  
DS232BQ Version 1.8  
© Future Technology Devices Intl. Ltd. 2005  
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