FT51A Advanced MCU with 8051 Compatible Core IC Datasheet
Version 1.5
Document No.: FT_000877
Clearance No.: FTDI#420
3.1.2.1
On-chip Debugger
The 8051 works with a high‐performance “Hardware Assisted Debugger” which manages the
communication between the core and the software.
3.1.2.2
UART / FTDI UART
There are two UARTs in the system – one designed by FTDI and the second incorporatedwithin the 8051
core. The 8051 UART has a maximum baud rate of up to 60kbps. The FTDI UART gives speeds up to
3Mbps.
When the data and control bus are configured in UART mode, the interface implements a standard
asynchronous serial UART port with full modem control. The UART can support baudrates from 183 baud
to 3 Mbaud. The maximum UART speed is limited by the CPU clock. The following maximum UART speed
applies:
CPU Frequency
48 MHz
Maximum UART Speed
3 Mbaud
24 MHz
3 Mbaud
12 MHz
1.5 Mbaud
3.2 Functional Block Descriptions
The following paragraphs detail each function within the FT51A. Please refer to the block diagram shown
in Figure 3-1 – FT51A Block Diagram.
3.2.1
8051 Ports 0 - 3
The 8051 core has four 8-bit bidirectional ports: P0, P1, P2 and P3. These ports can be fully or partially
mapped to external pins on the AIO and DIO bus. Firmware can change the pin mapping through IOMUX
programming. Table 3-1 shows the default pin mapping for all the 4 ports on the LQFP44 and WQFN48
packages.
PIN
TYPE
DESCRIPTION
AIO7 - AIO0
AIO15 - AIO8
DIO7 - DIO0
DIO15 - DIO8
Input / output P0.7 – P0.0
Input / output P2.7 – P2.0
Input / output P1.7 – P1.0
Input / output P3.7 – P3.0
Table 3-1 – 8051 Ports
3.2.2
Timers and Watchdog
Apart from standard 8051 timers the FT51A has four general purpose 16-bit timers A, B, C and D. A 32-
bit watchdog timer is also provided.
Copyright © Future Technology Devices International Limited
12
FTDI [ FUTURE TECHNOLOGY DEVICES INTERNATIONAL LTD. ]
