Document Reference No.: FT_000016
VDIP1 Vinculum VNC1L Module Datasheet Version 1.01
Clearance No.: FTDI# 131
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Appendix B – List of Figures and Tables
List of Figures
Figure 1.1- VDIP1.........................................................................................................................1
Figure 3.1 - VDIP1 Module Pin Out (Top View)..................................................................................4
Figure 3.2 – VDIP1 On-Board Jumper Pin Configuration....................................................................6
Figure 3.3 – SPI Slave Data Read Cycle...........................................................................................9
Figure 3.4 – SPI Slave Data Write Cycle. ....................................................................................... 10
Figure 3.5 – SPI Slave Data Timing Diagrams................................................................................. 11
Figure 3.6 - FIFO Read Cycle........................................................................................................ 13
Figure 3.7 - FIFO Write Cycle. ...................................................................................................... 14
Figure 5.1 VDIP1 Dimensions (Top View)....................................................................................... 16
Figure 5.2 VDIP1 Dimensions (Side View)...................................................................................... 16
Figure 6.1 Additional USB Port Configuration.................................................................................. 17
Figure 7.1 - Schematic Diagram ................................................................................................... 18
List of Tables
Table 3.1 - Pin Signal Descriptions..................................................................................................5
Table 3.2 - VDIP1 Port Selection Jumper Pins...................................................................................6
Table 3.4 - Default I/O Pin Configuration – UART Interface ................................................................8
Table 3.5 - Data and Control Bus Signal Mode Options – SPI Slave Interface........................................9
Table 3.6 - SPI Slave Data Timing ................................................................................................ 11
Table 3.7 - SPI Slave Status Register (ADD=’1’)............................................................................. 11
Table 3.8 - Default Interface I/O Pin Configuration Option – Paralle FIFO Interface ............................ 12
Table 3.9 FIFO Read Cycle Timing................................................................................................. 13
Table 3.10 - FIFO Write Cycle Timing ............................................................................................ 14
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