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VNC2-64Q1B 参数 Datasheet PDF下载

VNC2-64Q1B图片预览
型号: VNC2-64Q1B
PDF下载: 下载PDF文件 查看货源
内容描述: 的Vinculum - II嵌入式双USB主机控制器IC [VINCULUM-II EMBEDDED DUAL USB HOST CONTROLLER IC]
分类和应用: 控制器
文件页数/大小: 90 页 / 1976 K
品牌: FTDI [ FUTURE TECHNOLOGY DEVICES INTERNATIONAL LTD. ]
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Document No.: FT_000138  
VINCULUM-II EMBEDDED DUAL USB HOST CONTROLLER IC Datasheet  
Version - 1.2  
Clearance No.: FTDI# 143  
5.1 I/O Peripherals Signal Names  
Peripheral  
Debugger  
Signal Name  
Outputs Inputs Description  
debug_if  
uart_txd  
1
1
1
1
1
0
0
0
0
0
8
1
0
0
0
0
1
1
1
1
1
8
debugger interface  
Transmit asynchronous data output  
Request to send control output  
Data acknowledge (data terminal ready control) output  
Enable transmit data for RS485 designs  
Receive asynchronous data input  
Clear to send control input  
uart_rts#  
uart_dtr#  
uart_tx_active  
uart_rxd  
UART  
uart_cts#  
uart_dsr#  
uart_ri#  
Data request (data set ready control) input  
Ring indicator control input  
uart_dcd#  
fifo_data  
Data carrier detect control input  
FIFO data bus  
When high, do not write data into the FIFO. When low,  
data can be written into the FIFO by strobing WR high,  
then low.  
fifo_txe#  
1
0
When high, do not read data from the FIFO. When low,  
there is data available in the FIFO which can be read by  
strobing RD# low, then high.  
Writes the data byte on the D0...D7 pins into the  
transmit FIFO buffer when WR goes from high to low.  
Enables the current FIFO data byte on D0...D7 when  
low. Fetches the next FIFO data byte (if available) from  
the receive FIFO buffer when RD# goes from high to  
low  
fifo_rxf#  
fifo_wr#  
1
0
0
1
FIFO  
fifo_rd#  
0
1
fifo_oe#  
fifo_clkout  
gpio  
0
0
40  
0
0
1
1
0
0
1
1
1
1
0
1
1
8
1
1
40  
1
1
1
0
1
1
1
0
0
1
1
0
0
0
FIFO output enable synchronous FIFO only  
FIFO clock out synchronous FIFO only  
General purpose I/O  
GPIO  
spi_s0_clk  
spi_s0_ss#  
spi_s0_mosi  
spi_s0_miso  
spi_s1_clk  
spi_s1_ss#  
spi_s1_mosi  
spi_s1_miso  
spi_m_clk  
spi_m_mosi  
spi_m_miso  
spi_m_ss_0#  
spi_m_ss_1#  
pwm  
SPI clock input slave 0  
SPI chip select input slave 0  
SPI master out serial in slave 0  
SPI master in slave out slave 0  
SPI clock input slave 1  
SPI Slave  
0
SPI chip select input slave 1  
Master out slave in slave 1  
SPI Slave  
1
Master in slave out slave 1  
SPI clock input master  
Master out slave in - master  
SPI  
Master  
Master in slave out - master  
Active low slave select 0 from master to slave 0  
Active low slave select 1 from master to slave 1  
Pulse width modulation  
PWM  
Table 8 I/O Peripherals Signal Names  
Note: # is used to indicate an active low signal.  
Copyright © 2010 Future Technology Devices International Limited  
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