CS81 Series
(Continued)
• Hierarchical design environment for supporting large-scale circuits
• Simulation (before layout) considering the input slew rate and detailed RC delay calculation (after layout) ,
supporting development with minimized timing trouble after trial manufacture
• Support for memory (RAM/ROM) SCAN
• Support for memory (RAM) BIST
• Support for boundary SCAN
• Support for path delay test
• A variety of package options (TQFP, HQFP, EBGA, FBGA, TAB-BGA, FCBGA, LQFP)
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MACRO LIBRARY (Including macros being prepared)
1.
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Logic cells (about 400 types)
Adder
AND-OR Inverter
Clock Buffer
Latch
NAND
AND
NOR
SCAN Flip Flop
ENOR
AND-OR
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Decoder
Non-SCAN Flip Flop
Inverter
Buffer
OR-AND
OR-AND Inverter
OR
Selector
BUS Driver
EOR
Others
2. IP macros
CPU/DSP
High speed interface macros
Interface macro
Multimedia processing macros
Mixed signal macros
Compiled macros
PLL
FR, SPARClite, ARM7, ARM9, Communications DSP, DSP for AV
and others
622 Mbps to 780 Mbps, 2.5 Gbps to 3.125 Gbps
PCI, IEEE1394, USB, IrDA, and others
JPEG, MPEG, and others
ADC, DAC, OPAMP, and others
RAM, ROM, multiplier, adder, multiplier-accumulator, and others
Analog PLL, digital PLL
3. Special I/O interface macros
• T-LVTTL
• LVDS
• IEEE1394
• SSTL
• PCI
• SDRAM-I/F
• HSTL
• AGP
• P-CML
• USB
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FUJITSU [ FUJITSU COMPONENT LIMITED. ]
