AT1261
Low Quiescent Current/Voltage detectors
Functional Description
The following designators 1~6 refer to the timing diagram below.
1. While the input voltage (V
IN
) is higher than the detect voltage (V
DET-
), the output voltage at
V
OUT
pin equals the input voltage at V
IN
pin.
2. When the input V
IN
voltage falls lower than V
DET-
, V
OUT
drops near ground voltage.
3. If the input voltage decreases below the minimum operating voltage (V
MIN
), the V
OUT
output voltage
will be undefined.
4. During an increase of the input voltage from the V
SS
voltage, V
OUT
is undefined at the voltage below
V
MIN
. Exceeding the V
MIN
level, the output stays at the ground level (V
SS
) between the minimum
operating voltage (V
MIN
) and the detect release voltage (V
DET+
).
5. If the input voltage increases more than V
DET+
, the output voltage at V
OUT
pin equals the input
voltage at V
IN
pin.
6. The difference between V
DET+
and V
DET-
is the hysteresis in the system.
Input Voltage(V
IN
)
Detect Release Voltage(V
DET+
)
Detect Fail Voltage(V
DET-
)
Minimum Operating Voltage(V
MIN
)
Output Voltage(V
OUT
)
Ground Voltage(V
SS
)
(1)
(2)
(3)
(4)
(5)
(6)
Typical Application Circuit
R1
VIN VOUT
V
IN
VSS
V
OUT
V
IN
VSS
VIN VOUT
V
OUT
CMOS Output
N-Ch Open Drain Output
7F, No.9, PARK AVENUE II, Science-Based Industrial Park, Hsinchu 300, Taiwan, R.O.C.
Tel: 886-3-563-0878
Fax: 886-3-563-0879
WWW:
http://www.aimtron.com.tw
3/6/2007 REV:1.0
Email:
service@aimtron.com.tw
4
GMT [ GLOBAL MIXED-MODE TECHNOLOGY INC ]
