CD4070B, CD4077B
Functional Diagrams
CD4070B
1
2
5
6
8
9
12
13
10
4
CD4077B
1
2
5
6
8
9
12
13
10
4
A
J=A
⊕
B
K=C
⊕
D
M=G
⊕
H
L=E
⊕
F
B
C
D
E
F
G
H
3
J
A
B
3
J
K
⊕
B
K=C
⊕
D
J =A
M=G
L
C
D
E
F
G
H
K
L
V
SS
= 7
V
DD
= 14
⊕
H
=E
⊕
F
L
11
M
11
M
V
DD
V
DD
V
DD
V
DD
B
†
2(5,9,12)
p
p
n
V
SS
V
DD
A
†
1(6,8,13)
p
n
V
SS
V
DD
V
SS
V
SS
V
DD
V
SS
n
p
p
p
n
n
J
3(4,10,11)
A
†
1(6,8,13)
B
†
2(5,9,12)
p
n
V
SS
V
DD
p
n
n
n
n
p
n
p
J
3(4,10,11)
p
†
INPUTS PROTECTED
BY CMOS PROTECTION
NETWORK
†
INPUTS PROTECTED
BY CMOS PROTECTION
NETWORK
V
SS
V
SS
FIGURE 1. SCHEMATIC DIAGRAM FOR CD4070B
(1 OF 4 IDENTICAL GATES)
FIGURE 2. SCHEMATIC DIAGRAM FOR CD4077B
(1 OF 4 IDENTICAL GATES)
CD4070B TRUTH TABLE (1 OF 4 GATES)
A
0
1
0
1
NOTE:
1 = High Level
0 = Low Level
J=A
⊕
B
B
0
0
1
1
J
0
1
1
0
CD4077B TRUTH TABLE (1 OF 4 GATES)
A
0
1
0
1
NOTE:
1 = High Level
0 = Low Level
J=A
⊕
B
B
0
0
1
1
J
1
0
0
1
2
HARRIS [ HARRIS CORPORATION ]
