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HT12D(18DIP) 参数 Datasheet PDF下载

HT12D(18DIP)图片预览
型号: HT12D(18DIP)
PDF下载: 下载PDF文件 查看货源
内容描述: [Telecom Circuit, CMOS, PDIP18,]
分类和应用: LTE电信光电二极管电信集成电路
文件页数/大小: 11 页 / 141 K
品牌: HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
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HT12D/HT12F
Functional Description
Operation
The 2
12
series of decoders provides various combina-
tions of addresses and data pins in different packages
so as to pair with the 2
12
series of encoders.
The decoders receive data that are transmitted by an
encoder and interpret the first N bits of code period as
addresses and the last 12-N bits as data, where N is the
address code number. A signal on the DIN pin activates
the oscillator which in turn decodes the incoming ad-
dress and data. The decoders will then check the re-
ceived address three times continuously. If the received
address codes all match the contents of the decoder¢s
local address, the 12-N bits of data are decoded to acti-
vate the output pins and the VT pin is set high to indicate
a valid transmission. This will last unless the address
code is incorrect or no signal is received.
The output of the VT pin is high only when the transmis-
sion is valid. Otherwise it is always low.
Output type
Of the 2
12
series of decoders, the HT12F has no data
output pin but its VT pin can be used as a momentary
data output. The HT12D, on the other hand, provides 4
latch type data pins whose data remain unchanged until
new data are received.
Part
No.
HT12D
HT12F
Data
Pins
4
0
Address
Pins
8
12
Output
Type
Latch
¾
Operating
Voltage
2.4V~12V
2.4V~12V
N o
Flowchart
The oscillator is disabled in the standby state and acti-
vated when a logic
²high²
signal applies to the DIN pin.
That is to say, the DIN should be kept low if there is no
signal input.
P o w e r o n
S ta n d b y m o d e
D is a b le V T &
ig n o r e th e r e s t o f
th is w o r d
N o
C o d e in ?
Y e s
A d d r e s s b its
m a tc h e d ?
Y e s
S to re d a ta
N o
M a tc h
p r e v io u s s to r e d
d a ta ?
Y e s
3 tim e s
o f c h e c k in g
c o m p le te d ?
Y e s
L a tc h d a ta
to o u tp u t &
a c tiv a te V T
N o
A d d re s s o r
d a ta e rro r ?
Y e s
N o
Decoder timing
E n c o d e r
T r a n s m is s io n
E n a b le
E n c o d e r
D O U T
4 w o rd s
2
D e c o d e r V T
c h e c k
L a tc h e d
D a ta O u t
c h e c k
1 4
< 1 w o rd
c lo c k s
T r a n s m itte d
C o n tin u o u s ly
4 w o rd s
2
1 4
c lo c k s
Rev. 1.10
4
November 18, 2002