HT45R38
Functional Description
Execution Flow
The system clock for the microcontroller is derived from
either a crystal or an RC oscillator. The system clock is
internally divided into four non-overlapping clocks. One
instruction cycle consists of four system clock cycles.
Instruction fetching and execution are pipelined in such
a way that a fetch takes an instruction cycle while de-
coding and execution takes the next instruction cycle.
However, the pipelining scheme causes each instruc-
tion to effectively execute in a cycle. If an instruction
changes the program counter, two cycles are required to
complete the instruction.
Program Counter
-
PC
The program counter (PC) controls the sequence in
which the instructions stored in program ROM are exe-
cuted and its contents specify full range of program
memory.
After accessing a program memory word to fetch an in-
struction code, the contents of the program counter are
S y s te m
O S C 2 (R C
C lo c k
o n ly )
P C
P C
P C + 1
P C + 2
T 1
T 2
T 3
T 4
T 1
incremented by one. The program counter then points to
the memory word containing the next instruction code.
When executing a jump instruction, a conditional skip
execution, loading the PCL register, a subroutine call,
an initial reset, an internal interrupt, an external interrupt
or return from a subroutine, the PC manipulates the pro-
gram transfer by loading the address corresponding to
each instruction.
The conditional skip is activated by instructions. Once
the condition is met, the next instruction, fetched during
the current instruction execution, is discarded and a
dummy cycle replaces it to get the proper instruction.
Otherwise the program will proceed with the next in-
struction.
The lower byte of the program counter (PCL) is a read-
able and writable register (06H). Moving data into the
PCL performs a short jump. The destination must be
within the current Program Memory Page.
When a control transfer takes place, an additional
dummy cycle is required.
T 2
T 3
T 4
T 1
T 2
T 3
T 4
F e tc h IN S T (P C )
E x e c u te IN S T (P C -1 )
F e tc h IN S T (P C + 1 )
E x e c u te IN S T (P C )
F e tc h IN S T (P C + 2 )
E x e c u te IN S T (P C + 1 )
Execution Flow
Program Counter
*11
0
0
0
0
0
0
0
*11
*10
0
0
0
0
0
0
0
*10
*9
0
0
0
0
0
0
0
*9
#9
S9
*8
0
0
0
0
0
0
0
*8
#8
S8
*7
0
0
0
0
0
0
0
@7
#7
S7
*6
0
0
0
0
0
0
0
@6
#6
S6
*5
0
0
0
0
0
0
0
@5
#5
S5
*4
0
0
0
0
1
1
1
@4
#4
S4
*3
0
0
1
1
0
0
1
@3
#3
S3
*2
0
1
0
1
0
1
0
@2
#2
S2
*1
0
0
0
0
0
0
0
@1
#1
S1
*0
0
0
0
0
0
0
0
@0
#0
S0
Mode
Initial Reset
External Interrupt 0
External Interrupt 1
Timer/Event Counter 0 Overflow
External RC Oscillation Converter Interrupt
Timer/Event Counter 1 Overflow
A/D Converter Interrupt
Skip
Loading PCL
Jump, Call Branch
Return from Subroutine
Program Counter+2
#11 #10
S11 S10
Program Counter
Note: *11~*0: Program Counter bits
#11~#0: Instruction code bits
Rev. 1.00
7
S11~S0: Stack register bits
@7~@0: PCL bits
December 13, 2006
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
