250
t
P
– PROPAGATION DELAY – ns
200
V
CC
= 5 V
C1 (120 pF) PEAKING
CAPACITOR IS USED.
SEE FIGURE 5.
I
F
(mA)
5
3
1.6
C
L
= 15 pF INCLUDING PROBE
PULSE
AND JIG CAPACITANCES
.
GENERATOR
V
CC
Z
O
= 50
Ω
t
r
= t
f =
5 ns
V
O
HCPL-2200
1
+5 V
S1
D
1
619
Ω
150
t
PHL
1.6
3
5
V
CC 8
7
6
I
F
2
3
100
t
PLH
C
L
5 kΩ
D
2
D
3
D
4
S2
50
-60 -40 -20
4
GND
5
0
20
40
60
80 100
T
A
– TEMPERATURE – °C
INPUT V
C
MONITORING
NODE
D
1-4
ARE 1N916 OR 1N3064.
Figure 6. Typical Propagation Delays
vs. Temperature.
INPUT
V
E
t
PZL
1.3 V
t
PLZ
0.5 V
0.5 V
1.3 V
0V
t
PHZ
3.0 V
1.3 V
0V
S1 AND
S2 CLOSED
V
OL
V
OH
≈1.5
V
S1 AND
S2 CLOSED
OUTPUT S1 CLOSED
V
O
S2 OPEN
t
PZH
OUTPUT
V
O
S1 OPEN
S2 CLOSED
Figure 7. Test Circuit for t
PHZ
, t
PZH
, t
PLZ
, and t
PZL
.
T
p
– ENABLE PROPAGATION DELAY – ns
t
P
– ENABLE PROPAGATION DELAY – ns
100
C
L
= 15 pF
80
V
CC
20 V
4.5 V
200
C
L
= 15 pF
tr
,
tf
– RISE, FALL TIME – ns
120
V
CC
150
t
PHZ
100
80
60
V
CC
= 5 V
C
2
= 15 pF
20 V
4.5 V
60
t
PLZ
20 V
100
40
t
PZL
20
0
-60 -40 -20
4.5 V
tr
20 V
50
t
PZH
40
20
tf
4.5 V
0
20
40
60
80 100
0
-60 -40 -20
0
20
40
60
80 100
0
-60 -40 -20
0
20
40
60
80 100
T
A
– TEMPERATURE – °C
T
A
– TEMPERATURE – °C
T
A
– TEMPERATURE – °C
Figure 8. Typical Logic Low Enable
Propagation Delay vs. Temperature.
Figure 9. Typical Logic High Enable
Propagation Delay vs. Temperature.
Figure 10. Typical Rise, Fall Time vs.
Temperature.
1-129
HP [ AGILENT(HEWLETT-PACKARD) ]
