Product Part Number: IBM22-ALDC1005S
Document Number: DCALD5DSU-04
ALDC1-5S
Data Compression
I B M Microelectronics
Chapter 2. Functional Description
ALDC1-5S provides a microprocessor interface,
an original data interface, a compressed data
interface, and a clock input.
Internal to ALDC1-5S are the ALDC encoder,
ALDC decoder, and the ALDC1-5S registers.
Figure 2-1 shows these functional areas.
↑
DMA Device
↓
µP
µP
Interface
Original Data
Interface
2.1.2 Original Data Interface
The original data interface accepts data for
compression and provides decompressed data
to an external DMA device connected to it.
The original data interface counts the bytes of
original data received during compression
operations and the bytes of decompressed data
sent during decompression operations. This
count is available in the Original Data Interface
Transfer Count (TCO) register.
Section 4.2 on page 4-4 describes the original
data interface timing in detail.
↑
↓
Registers
↑
↓
ALDC
Encoder
C
A
M
ALDC
Decoder
R
A
M
2.1.3 Compressed Data Interface
The compressed data interface accepts com-
pressed data for decompression from an
external DMA controller connected to it. The
compressed data interface provides com-
pressed data to the external DMA controller.
The compressed data interface counts the bytes
of compressed data received during decom-
pression operations and the bytes of com-
pressed data sent during compression
operations. This count is available in the Com-
pressed Data Interface Transfer Count (TCC)
register.
The compressed data interface buffers data
during data transfer operations in a sixteen-
byte FIFO.
The compressed data interface operates in
burst mode
which makes bytes available to the
external DMA controller in a stream.
Section 4.3 on page 4-7 describes the com-
pressed data interface timing in detail.
clock
Clock
Generation
↑
↓
Compressed Data
Interface
↑
↓
DMA Controller
Figure
2-1. ALDC1-5S Functional Areas
2.1 Functional Areas
2.1.1 Microprocessor Interface
The microprocessor interface allows a micro-
processor to query status and control
ALDC1-5S. The ALDC1-5S registers are
externally accessible through the micro-
processor interface. These registers provide
the primary means by which ALDC1-5S and the
microprocessor communicate.
Section 4.1 on page 4-1 describes the micro-
processor interface timing in detail. Section 3.1
on page 3-1 describes the ALDC1-5S registers
in detail.
2.1.4 Clock Generation
The clock generation circuitry accepts a single
clock input. It generates all internal clocks nec-
essary for ALDC1-5S to function.
Section 4.4 on page 4-10 describes the clock
timing in detail.
(C) IBM CORP. 1993, 1994. ALL RIGHTS RESERVED. USE IS FURTHER SUBJECT TO THE PROVISIONS ON THE BACK OF THE TITLE PAGE.
2-1
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