IBM0418A4ACLAA IBM0418A8ACLAA
IBM0436A8ACLAA IBM0436A4ACLAA
8Mb (256Kx36 & 512Kx18) and 4Mb (128Kx36 & 256Kx18) SRAM
AC Characteristics (TA = 0 to +85°C, VDD = 3.3V -5%, +5%, VDDQ = 1.9V, Clocks run from 0.9 to 1.7V, VREF
=
0.85).
-4P
-4F
-4H
-5
-5H
Parameter
Symbol
Units Notes
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
t
Cycle Time
4.2
1.5
1.5
—
—
—
4.3
1.5
1.5
—
—
—
4.5
1.5
1.5
—
—
—
5.0
1.5
1.5
—
—
—
5.5
1.5
1.5
—
—
—
ns
ns
ns
KHKH
t
Clock High Pulse Width
Clock Low Pulse Width
Clock High to Output Valid
Clock Low to Output Valid
Address Setup Time
KHKL
t
—
—
—
—
—
KLKH
t
1
1
4.2
1.9
—
4.3
1.9
—
4.5
2.0
—
5.0
2.25
—
5.5
2.5
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
KHQV
t
—
—
—
—
—
KLQV
t
3
0.4
0.8
0.4
0.8
0.4
0.8
0.4
0.8
0.7
0.7
1.0
—
0.4
0.8
0.4
0.8
0.4
0.8
0.4
0.8
0.5
0.5
1.0
—
0.5
1.0
0.5
1.0
0.5
1.0
0.5
1.0
0.5
0.5
—
0.5
1.0
0.5
1.0
0.5
1.0
0.5
1.0
0.5
0.5
—
0.5
1.0
0.5
1.0
0.5
10
AVKH
t
3
Address Hold Time
—
—
—
—
—
KHAX
t
3
Sync Select Setup Time
Sync Select Hold Time
Write Enables Setup Time
Write Enables Hold Time
Data In Setup Time
—
—
—
—
—
SVKH
t
3
—
—
—
—
—
KHSX
t
3
—
—
—
—
—
WVKH
t
3
—
—
—
—
—
KHWX
t
3
—
—
—
—
0.5
1.0
0.5
0.5
—
—
DVKH
t
3
Data In Hold Time
—
—
—
—
—
KHDX
t
1, 4
1, 4
1, 4
1, 4
1
Clock Low to Data Out Hold Time
Clock Low to Output Active
Clock High to Output High-Z
Output Enable to High-Z
Output Enable to Low-Z
Output Enable to Output Valid
Output Enable Setup Time
Output Enable Hold TIme
Sleep Mode Recovery TIme
Sleep Mode Enable TIme
—
—
—
—
—
KLQX
t
—
—
—
—
—
KLQX4
t
2.5
2.5
—
2.5
2.5
—
2.5
2.5
—
2.5
2.5
—
2.5
2.5
—
KHQZ
t
—
—
—
GHQZ
t
0.5
—
0.5
—
0.5
—
0.5
—
0.5
—
GLQX
t
1
1.8
—
1.8
—
1.8
—
1.8
—
1.8
—
GLQV
t
1, 2
1, 2
0.5
1.5
200
—
0.5
1.5
200
—
0.5
1.5
200
—
0.5
1.5
200
—
0.5
1.5
200
—
GHKH
t
—
—
—
—
—
KHGX
t
—
—
—
—
—
ZZR
t
9.0
9.0
9.0
10.0
11.0
ZZE
1. See the AC Test Loading figure on page 11.
2. Output Driver Impedance update specifications for G induced updates. Write and Deselect cycles will also induce Output Driver
updates during High-Z.
3. During normal operation, V ,V ,T
, and T
of inputs must be within 20% of V , V , T
, and T
of Clock.
FALL
IH IL RISE
FALL
IH
IL RISE
4. Verified by design and tested without guardbands.
trlh3320.04
01/01
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 12 of 26
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