X24165
Page Write
The X24165 is capable of a 32 byte page write operation.
It is initiated in the same manner as the byte write
operation, but instead of terminating the write cycle after
the first data word is transferred, the master can
transmit up to fifteen more words. After the receipt of
each word, the X24165 will respond with an acknowledge.
After the receipt of each word, the five low order ad- dress
bits are internally incremented by one. The high order bits
of the word address remain constant. If the master should
transmit more than 32 words prior to generating the
stop condition, the address counter will “roll over” and
the previously written data will be over- written. As with
the byte write operation, all inputs are disabled until
completion of the internal write cycle. Refer to Figure 6
for the address, acknowledge and data transfer sequence.
Flow 1. ACK Polling Sequence
WRITE OPERATION
COMPLETED
ENTER ACK POLLING
ISSUE
START
ISSUE SLAVE
ADDRESS AND R/W = 0
ISSUE STOP
ACK
RETURNED?
NO
YES
Acknowledge Polling
The Max Write Cycle Time can be significantly reduced
using Acknowledge Polling. To initiate Acknowledge
Polling, the master issues a start condition followed by
the Slave Address Byte for a write or read operation. If
the device is still busy with the high voltage cycle, then
no ACK will be returned. If the device has completed
the write operation, an ACK will be returned and the
host can then proceed with the read or write operation.
NEXT
OPERATION
NO
A WRITE?
YES
ISSUE BYTE
ADDRESS
ISSUE STOP
Refer to Flow 1.
PROCEED
PROCEED
6551 ILL F09
Figure 6. Page Write
S
T
A
R
T
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
WORD ADDRESS (n)
DATA n
DATA n+1
DATA n+31
S
T
O
P
SDA LINE
BUS ACTIVITY:
X24165
S
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
P
6551 ILL F10.1
6
ICMIC [ IC MICROSYSTEMS ]
