X24165
Bus Timing
t
t
t
t
HIGH
LOW
R
F
SCL
t
t
t
t
t
SU:STA
HD:STA
HD:DAT
SU:DAT
SU:STO
SDA IN
t
t
t
AA
DH
BUF
SDA OUT
6551 ILL F17
Write Cycle Limits
Symbol
(5)
Typ.
Parameter
Min.
Max.
Units
(6)
tWR
Write Cycle Time
5
10
ms
6551 FRM T11.1
The write cycle time is the time from a valid stop
condition of a write sequence to the end of the internal
X24165 bus interface circuits are disabled, SDA is
allowed to remain HIGH, and the device does not
erase/program cycle. During the write cycle, the
respond to its slave address.
Bus Timing
SCL
ACK
SDA
8th BIT
WORD n
t
WR
6551 ILL F18
STOP
CONDITION
START
CONDITION
Notes: (5)Typical values are for TA = 25°C and nominal supply voltage (5V).
(6)tWR is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum
time the device requires to automatically complete the internal write operation.
SYMBOL TABLE
Guidelines for Calculating Typical Values of
Bus Pull-Up Resistors
WAVEFORM
INPUTS
OUTPUTS
120
V
CC MAX
Must be
steady
Will be
steady
R
=1.8KΟ
=
MIN
I
100
80
OL MIN
t
R
R
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
=
MAX
C
BUS
MAX.
RESISTANCE
60
40
20
0
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
MIN.
RESISTANCE
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
20 40 60 80100120
BUS CAPACITANCE (pF)
0
N/A
Center Line
is High
Impedance
6551 ILL F19
13
ICMIC [ IC MICROSYSTEMS ]
