X24320
WRITE OPERATIONS
Byte Write
For a write operation, the device requires the Slave
Address Byte, the Word Address Byte 1, and the Word
Address Byte 0, which gives the master access to any one
of the words in the array. Upon receipt of the Word
Address Byte 0, the device responds with an acknowledge,
and waits for the first eight bits of data. After
receiving the 8 bits of the data byte, the device again
responds with an acknowledge. The master then
terminates the transfer by generating a stop condition, at
which time the device begins the internal write cycle
to the nonvolatile memory. While the internal write cycle
is in progress the device inputs are disabled
and the device will not respond to any requests from the
master. The SDA pin is at high impedance. See
figure 5.
Page Write
The device is capable of a thirty-two byte page write
operation. It is initiated in the same manner as the byte
write operation; but instead of terminating the write
operation after the first data word is transferred, the
master can transmit up to thirty-one more words. The device
will respond with an acknowledge after the
receipt of each word, and then the byte address is
internally incremented by one. The page address
remains constant. When the counter reaches the end of the
page, it “rolls over” and goes back to the first byte of the
current page. This means that the master can write 32 words
to the page beginning at any byte.
If the master begins writing at byte 16, and loads 32 words,
then the first 16 words are written to bytes 16
through 31, and the last 16 words are written to bytes
0 through 15. Afterwards, the address counter would
point to byte 16. If the master writes more than 32 words,
then the previously loaded data is overwritten
by the new data, one byte at a time.
The master terminates the data byte loading by
issuing a stop condition, which causes the device to
begin the nonvolatile write cycle. As with the byte write
operation, all inputs are disabled until completion of
the internal write cycle. Refer to figure 6 for the
address, acknowledge, and data transfer sequence.
Figure 5. Byte Write Sequence
S
T
SIGNALS
FROM THE
MASTER
A
R
SLAVE
ADDRESS
WORD ADDRESS
BYTE 1
WORD ADDRESS
BYTE 0
DATA
S
T
O
P
T
SDA BUS
SIGNALS
FROM THE
SLAVE
S1010
0
A
C
A
C
A
C
A
C
P
K
K
K
K
7035 FM 07
Figure 6. Page Write Sequence
(0=n=31)
SIGNALS
FROM THE
MASTER
S
T
A
R
SLAVE
ADDRESS
WORD ADDRESS
BYTE 1
WORD ADDRESS
BYTE 0
DATA
(0)
DATA
(n)
S
T
O
P
T
SDA BUS
SIGNALS
FROM THE
SLAVE
S 1010
0
A
C
A
C
A
C
A
C
A
C
P
K
K
K
K
K
7035 FM 08
6
ICMIC [ IC MICROSYSTEMS ]
