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X24C01AS8MG-3 参数 Datasheet PDF下载

X24C01AS8MG-3图片预览
型号: X24C01AS8MG-3
PDF下载: 下载PDF文件 查看货源
内容描述: 串行E2PROM [Serial E2PROM]
分类和应用: 内存集成电路光电二极管可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟
文件页数/大小: 13 页 / 272 K
品牌: ICMIC [ IC MICROSYSTEMS ]
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X24C01A
DEVICE ADDRESSING
Following a start condition the master must output the
address of the slave it is accessing. The most significant
four bits of the slave address are the device type
identifier (see Figure 4). For the X24C01A this is fixed as
Following the start condition, the X24C01A monitors the
SDA bus comparing the slave address being transmitted
with its slave address (device type and state of A
0
,
A
2
inputs). Upon a correct compare the X24C01A
A
1
and
1010[B].
Figure 4. Slave Address
DEVICE TYPE
IDENTIFIER
outputs an acknowledge on the SDA line. Depending on the
state of the R/W bit, the X24C01A will execute a read
or write operation.
WRITE OPERATIONS
Byte Write
For a write operation, the X24C01A requires a second
address field. This address field is the word address,
comprised of eight bits, providing access to any one of the
128 words of memory. Note: the most significant bit
1
0
1
0
A2
A1
A0
R/W
DEVICE
ADDRESS
3841 FHD F08
is a don’t care. Upon receipt of the word address the
X24C01A responds with an acknowledge, and awaits
the next eight bits of data, again responding with an
acknowledge. The master then terminates the transfer
by generating a stop condition, at which time the X24C01A
begins the internal write cycle to the nonvolatile memory.
The next three significant bits address a particular
device. A system could have up to eight X24C01A
devices on the bus (see Figure 10). The eight addresses are
defined by the state of the A
0
, A
1
and A
2
inputs.
The last bit of the slave address defines the operation to be
performed. When set to one a read operation is
While the internal write cycle is in progress the X24C01A
inputs are disabled, and the device will not respond to
any requests from the master. Refer to Figure 5 for the
address, acknowledge and data transfer sequence.
selected, when set to zero a write operation is selected.
Figure 5. Byte Write
S
T
BUS ACTIVITY:
MASTER
A
R
SLAVE
ADDRESS
WORD
ADDRESS
DATA
S
T
O
P
T
S
A
C
A
C
A
C
SDA LINE
BUS ACTIVITY:
X24C01A
P
K
K
K
3841 FHD F09
Figure 6. Page Write
S
T
BUS ACTIVITY:
MASTER
A
R
SLAVE
ADDRESS
WORD ADDRESS n
DATA n
DATA n–1
DATA n+3
S
T
O
P
T
S
A
C
A
C
A
C
A
C
A
C
SDA LINE
BUS ACTIVITY:
X24C01A
P
K
K
K
K
K
3841 FHD F10
NOTE: In this example n = xxxx 0000 (B); x = 1 or 0
4