X24C01
WRITE CYCLE LIMITS
(5)
Symbol
Parameter
Write Cycle Time
Min.
Typ.
Max.
Units
(6)
tWR
5
10
ms
3837 PGM T08
The write cycle time is the time from a valid stop
condition of a write sequence to the end of the internal
erase/program cycle. During the write cycle, the X24C01
bus interface circuits are disabled, SDA is allowed to remain
high, and the device does not respond to its word address.
Write Cycle Timing
SCL
ACK
SDA
8th BIT
WORD n
t
WR
STOP
CONDITION
START
CONDITION
X24C01
ADDRESS
3837 FHD F05
Notes: (5) Typical values are for TA = 25°C and nominal supply voltage (5V).
(6) tWR is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum
time the device requires to automatically complete the internal write operation.
SYMBOL TABLE
Guidelines for Calculating Typical Values of
Bus Pull-Up Resistors
WAVEFORM
INPUTS
OUTPUTS
120
V
Must be
steady
Will be
steady
CC MAX
R
=
=2.6KΟ
MIN
I
100
80
OL MIN
t
May change
from Low to
High
Will change
from Low to
High
R
R
=
MAX
C
BUS
MAX.
RESISTANCE
60
40
20
0
May change
from High to
Low
Will change
from High to
Low
MIN.
RESISTANCE
Changing:
State Not
Known
Don’t Care:
Changes
Allowed
20 40 60 80100120
BUS CAPACITANCE (pF)
0
Center Line
is High
Impedance
N/A
3837 FHD F15
10
ICMIC [ IC MICROSYSTEMS ]
