X24C04
Current Address Read
Internally the X24C04 contains an address counter that
maintains the address of the last word accessed,
incremented by one. Therefore, if the last access (either a
read or write) was to address n, the next read operation
would access data from address n + 1. Upon receipt of the
slave address with the R/W bit set to one, the
X24C04 issues an acknowledge and transmits the eight bit
word. The read operation is terminated by the master;
by not responding with an acknowledge and by issuing a
stop condition. Refer to Figure 7 for the sequence of
Random Read
Random read operations allow the master to access any
memory location in a random manner. Prior to issuing
the slave address with the R/W bit set to one, the master
must first perform a “dummy” write opera-
tion. The master issues the start condition, and the slave
address followed by the word address it is to read.
After the word address acknowledge, the master
immediately reissues the start condition and the slave
address with the R/W bit set to one. This will be followed by
an acknowledge from the X24C04 and then by the
eight bit word. The read operation is terminated by the
master; by not responding with an acknowledge and by
issuing a stop condition. Refer to Figure 8 for the
address, acknowledge and data transfer sequence.
address, acknowledge and data transfer.
Figure 7. Current Address Read
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T
BUS ACTIVITY:
MASTER
A
R
SLAVE
ADDRESS
DATA
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O
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A
C
SDA LINE
BUS ACTIVITY:
X24C04
P
K
3839 FHD F13
Figure 8. Random Read
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BUS ACTIVITY:
MASTER
A
R
SLAVE
ADDRESS
WORD
ADDRESS n
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T
A
R
SLAVE
ADDRESS
DATA n
S
T
O
P
T
S
A
C
A
C
T
S
A
C
SDA LINE
BUS ACTIVITY:
X24C04
P
K
K
K
3839 FHD F14
7
ICMIC [ IC MICROSYSTEMS ]
