X24C08
Flow 1. ACK Polling Sequence
WRITE OPERATION
COMPLETED
Page Write
The X24C08 is capable of a sixteen byte page write
operation. It is initiated in the same manner as the byte
write operation, but instead of terminating the write cycle after
the first data word is transferred, the master can
ENTER ACK POLLING
transmit up to fifteen more words. After the receipt of each
word, the X24C08 will respond with an acknowl-
edge.
After the receipt of each word, the four low order address bits
are internally incremented by one. The high order six
bits of the word address remain constant. If the master
should transmit more than sixteen words prior to gener-
ating the stop condition, the address counter will “roll over”
and the previously written data will be overwritten.
As with the byte write operation, all inputs are disabled until
completion of the internal write cycle. Refer to
Figure 6 for the address, acknowledge and data transfer
sequence.
Acknowledge Polling
The disabling of the inputs can be used to take advan- tage
of the typical 5 ms write cycle time. Once the stop
condition is issued to indicate the end of the host’s write
operation the X24C08 initiates the internal write cycle.
ACK polling can be initiated immediately. This involves
issuing the start condition followed by the slave address
for a write operation. If the X24C08 is still busy with the write
operation no ACK will be returned. If the X24C08
has completed the write operation an ACK will be
returned and the host can then proceed with the next
ISSUE
START
ISSUE SLAVE
ADDRESS AND R/W = 0
ISSUE STOP
ACK
RETURNED?
NO
YES
NEXT
OPERATION
NO
A WRITE?
YES
ISSUE STOP
ISSUE BYTE
ADDRESS
PROCEED
read or write operation. Refer to Flow 1.
PROCEED
3842 FHD F11
Figure 6. Page Write
S
T
BUS ACTIVITY:
MASTER
A
R
T
S
SLAVE
ADDRESS
WORD ADDRESS n
DATA n
DATA n+1
DATA n+15
S
T
O
P
SDA LINE
BUS ACTIVITY:
X24C08
P
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
3842 FHD F12
NOTE: In this example n = xxxx 000 (B); x = 1 or 0
6
ICMIC [ IC MICROSYSTEMS ]
