X24C08
DEVICE ADDRESSING
The last bit of the slave address defines the operation to be
performed. When set to one a read operation is
Following a start condition the master must output the
address of the slave it is accessing. The most significant
selected, when set to zero a write operation is selected.
four bits of the slave address are the device type
identifier (see Figure 4). For the X24C08 this is fixed as
1010[B].
Following the start condition, the X24C08 monitors the
SDA bus comparing the slave address being transmit-
ted with its slave address (device type and state of A2
input.) Upon a correct compare the X24C08 outputs an
Figure 4. Slave Address
acknowledge on the SDA line. Depending on the state of
the R/W bit, the X24C08 will execute a read or write
HIGH
ORDER
WORD
ADDRESS
operation.
DEVICE TYPE
IDENTIFIER
WRITE OPERATIONS
1
0
1
0
A2
A1
A0 R/W
Byte Write
For a write operation, the X24C08 requires a second
address field. This address field is the word address,
DEVICE
ADDRESS
3842 FHD F09
comprised of eight bits, providing access to any one of
1024 words in the array. Upon receipt of the word
address the X24C08 responds with an acknowledge, and
awaits the next eight bits of data, again responding
The next bit addresses a particular device. A system could
have up to two X24C08 devices on the bus (see
with an acknowledge. The master then terminates the
transfer by generating a stop condition, at which time the
Figure 10). The two addresses are defined by the state of
the A2 input.
X24C08 begins the internal write cycle to the nonvolatile
memory. While the internal write cycle is in progress the
The next two bits of the slave address field are an
extension of the array’s address and are concatenated
X24C08 inputs are disabled, and the device will not
respond to any requests from the master. Refer to
with the eight bits of address in the word address field,
providing direct access to the whole 1024 x 8 array.
Figure 5 for the address, acknowledge and data transfer
sequence.
Figure 5. Byte Write
S
T
S
T
SLAVE
WORD
ADDRESS
A
BUS ACTIVITY:
ADDRESS
DATA
R
T
MASTER
O
P
SDA LINE
S
P
A
C
K
A
C
K
A
C
K
BUS ACTIVITY:
X24C08
3842 FHD F10
5
ICMIC [ IC MICROSYSTEMS ]
