X24C08
WRITE CYCLE LIMITS
Symbol
(5)
Typ.
Parameter
Min.
Max.
Units
(6)
tWR
Write Cycle Time
5
10
ms
3842 PGM T08
The write cycle time is the time from a valid stop
condition of a write sequence to the end of the internal
bus interface circuits are disabled, SDA is allowed to remain
high, and the device does not respond to its slave
erase/program cycle. During the write cycle, the X24C08
address.
Write Cycle Timing
SCL
ACK
SDA
8th BIT
WORD n
t
WR
STOP
CONDITION
START
CONDITION
X24C08
ADDRESS
3842 FHD F05
Notes:(5) Typical values are for T
(6) t
= 25°C and nominal supply voltage (5V).
A
is the minimum cycle time from the system perspective when polling techniques are not used. It is the maximum time the device
WR
requires to perform the internal write operation.
SYMBOL TABLE
Guidelines for Calculating Typical Values of Bus
Pull-Up Resistors
WAVEFORM
INPUTS
OUTPUTS
120
V
Must be
steady
Will be
steady
CC MAX
R
=
=1.8KΟ
MIN
I
100
80
OL MIN
t
MAX
R
May change
from Low to
High
Will change
from Low to
High
R
=
MAX
C
BUS
MAX.
RESISTANCE
60
40
20
0
May change
from High to
Low
Will change
from High to
Low
MIN.
RESISTANCE
Changing:
State Not
Known
Don’t Care:
Changes
Allowed
20 40
60 80100120
0
Center Line
is High
Impedance
BUS CAPACITANCE (pF)
N/A
3842 FHD F17
11
ICMIC [ IC MICROSYSTEMS ]
