Integrated
Circuit
Systems, Inc.
ICS843021
F
EMTO
C
LOCKS
™ C
RYSTAL
-
TO
-
3.3V LVPECL C
LOCK
G
ENERATOR
output frequency. The C1 = 27pF and C2 = 33pF are recom-
mended for frequency accuracy. For different board layout, the
C1 and C2 values may be slightly adjusted for optimizing fre-
quency accuracy.
A
PPLICATION
S
CHEMATIC
Figure 3A
shows a schematic example of the ICS843021. An
example of LVEPCL termination is shown in this schematic.
Additional LVPECL termination approaches are shown in the
LVPECL Termination Application Note. In this example, an 18pF
parallel resonant 25MHz crystal is used for generating 125MHz
VCC
R2
10
VCCA
VCC
C3
10uF
C4
0.01u
U1
Q
1
2
3
4
VCCA
VEE
XTAL_OUT
XTAL_IN
VCC
Q0
nQ0
NC
8
7
6
5
VCC
+
Zo = 50 Ohm
R3
133
R5
133
C2
33pF
25MHz
18pF
Zo = 50 Ohm
nQ
X1
-
ICS843021
ICS843011
C5
0.1u
R4
82.5
R6
82.5
C1
27pF
VCC=3.3V
F
IGURE
3A. ICS843021 S
CHEMATIC
E
XAMPLE
PC B
OARD
L
AYOUT
E
XAMPLE
Figure 3B
shows an example of ICS843021 P.C. board layout.
The crystal X1 footprint shown in this example allows installa-
tion of either surface mount HC49S or through-hole HC49 pack-
age. The footprints of other components in this example are listed
in the
Table 6.
There should be at least one decoupling capacitor
per power pin. The decoupling capacitors should be located as
close as possible to the power pins. The layout assumes that
the board has clean analog power ground plane.
T
ABLE
6. F
OOTPRINT
T
ABLE
Reference
C1, C2
C3
C4, C5
Size
0402
0805
0603
R2
0603
NOTE: Table 6, lists component
sizes shown in this layout example.
F
IGURE
3B. ICS843021 PC B
OARD
L
AYOUT
E
XAMPLE
843021AG
www.icst.com/products/hiperclocks.html
7
REV. C MARCH 31, 2005