ICS2008B
Pin Descriptions
PIN NUMBER
TQFP PLCC
PIN
NAME
TYPE
DESCRIPTION
Video inputs from camera or other source. NOTE: This is also the Y
(Luma) input for S-VHS and HI-8 systems.
C (Chroma) inputs for S-VHS and HI-8 systems. In NTSC systems, this
pin should be tied to its respective Y input.
12, 10 18, 16 Y1, Y2
AI
AI
11, 9
17, 15 C1, C2
15
13
14
8
21
19
20
14
13
3
DTHRESH
AI
AI
Data Threshold bypass input.
STHRESH
CTHRESH
Y OUT
C OUT
FRAME
CLICK
LTCIN+
LTCIN–
LTCOUT
LRCLK
VITCOUT
VITCGATE
TxD
SYNC Threshold bypass input.
Clamp Threshold bypass input.
Video output. This is also the Y (Luma) output in S-Video mode.
C (Chroma) output for S-VHS and HI-8 systems.
Color Frame A/B input. This input is self biased (See Applications).
LTC SYNC input. This input is self biased (See Applications).
SMPTE LTC input+. This input is self biased (See Applications).
SMPTE LTC input–. This input is self biased (See Applications).
SMPTE LTC output
AI
AO
AO
AI
7
41
42
44
43
1
4
AI
AI
AI
AO
O
O
O
O
I
6
5
7
20
22
21
18
16
17
19
4
26
28
27
24
22
23
25
10
9
SMPTE LTC receive clock output.
SMPTE VITC output to video mixer circuit.
VITC gate indicates VITC code is being output for video overlay.
UART Transmit data
RxD
UART Receive data
CTS*
I
Clear to Send
RTS*
O
I
O
AI
I
Ready to Send
14.318 MHz crystal input.
14.318 MHz crystal oscillator output.
Tie to +5 VDC
XTAL1
XTAL2
LFC
3
2
8
24, 23 30, 29 A1-A0
Address bus
27
30
25
26
40
33
36
31
32
2
IOR*
I
Read Enable (active low)
IOW*
I
Write Enable (active low)
SMPTECS*
UARTCS*
RESET
I
I
SMPTE port chip select (active low)
UART chip select (active low)
Master reset (active high)
I
38–31 44–37 D7-D0
I/O
O
P
Bi-directional data bus
39
5
1
INTR
AVDD
AVSS
VDD
VSS
Interrupt Request (active high)
Analog VDD
11
12
35
34
6
P
Analog Ground
29
28
P
Digital VDD
P
Digital
TYPE:
A – Analog • P – Power • I – Input • O – Output 2008 2008B ICS2008
ICS2008B Rev D 4/05/05
3
ICSI [ INTEGRATED CIRCUIT SOLUTION INC ]
