IDT49FCT805/A
FAST CMOS BUFFER/CLOCK DRIVER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS
V
CC
7V
500
Pulse
Generator
V
IN
D.U.T.
50pF
R
T
500
C
L
V
OUT
SWITCH POSITION
Test
Disable LOW
Enable LOW
Disable HIGH
Enable HIGH
Switch
Closed
GND
DEFINITIONS:
C
L
= Load capacitance: includes jig and probe capacitance.
R
T
= Termination resistance: should be equal to Z
OUT
of the Pulse Generator.
Test Circuits for All Outputs
3V
1.5V
INPUT
t
P LH
t
PHL
V
OH
2.0V
OUTPUT
t
R
t
F
OUTPUT 2
t
PLH2
3V
1.5V
INPUT
t
PLH
t
PHL
V
OH
1.5V
OUTPUT
t
SK
(p) = t
PHL
-
t
PLH
V
OL
INPUT
t
PLH1
t
PHL1
3V
1.5V
0V
V
OH
PACKAGE 1
OUTPUT
ENABLE
CONTROL
INPUT
t
PZL
OUTPUT
NORMALLY
LOW
OUTPUT
NORMALLY
HIGH
3.5V
SW ITCH
CLO SED
3V
1.5V
INPUT
t
PLH 1
t
PLH 1
0V
V
OH
1.5V
0V
1.5V
V
OL
OUTPUT 1
t
SK (o)
t
SK (o)
V
OL
V
OH
1.5V
V
OL
t
PHL2
or
0.8V
Package Delay
t
SK
(o) = t
PLH2
-
t
PLH1
t
PHL2
-
t
PHL1
0V
Output Skew
Pulse Skew - t
SK(P)
1.5V
V
O L
t
SK (pp)
t
SK(pp)
V
OH
1.5V
V
O L
t
PLH 2
t
SK
(pp) = t
PLH2
-
t
PLH1
or
DISABLE
3V
1.5V
0V
3.5V
t
PLZ
PACKAGE 2
OUTPUT
t
PHL2
t
PH L2
-
t
PHL1
1.5V
t
PHZ
1.5V
0V
0.3V V
OL
t
P ZH
SW ITCH
O PEN
0.3V V
OH
0V
Part-to-Part Skew - t
SK(PP)
NOTE:
1. Package 1 and Package 2 are same device type and speed grade.
Enable and Disable Times
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH
2. Pulse Generator for All Pulses: Rate
≤
1.0MHz; t
F
≤
2.5ns; t
R
≤
2.5ns
6
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
