DATASHEET
Two Output Differential Buffer for PCIe Gen3
Recommended Application:
2 output PCIe Gen3 zero-delay/fanout buffer
General Description:
The 9DB233 zero-delay buffer supports PCIe Gen3
requirements, while being backwards compatible to PCIe
Gen2 and Gen1. The 9DB233 is driven by a differential SRC
output pair from an IDT 932S421 or 932SQ420 or equivalent
main clock generator. It attenuates jitter on the input clock
and has a selectable PLL bandwidth to maximize
performance in systems with or without Spread-Spectrum
clocking. An SMBus interface allows control of the PLL
bandwidth and bypass options, while 2 clock request (OE#)
pins make the 9DB233 suitable for Express Card
applications.
Key Specifications:
•
Cycle-to-cycle jitter < 50 ps
•
Output-to-output skew < 50 ps
•
PCIe Gen3 phase jitter < 1.0ps RMS
9DB233
Features/Benefits:
•
OE# pins/Suitable for Express Card applications
•
PLL or bypass mode/PLL can dejitter incoming clock
•
Selectable PLL bandwidth/minimizes jitter peaking in
downstream PLL's
•
Spread Spectrum Compatible/tracks spreading input
clock for low EMI
•
SMBus Interface/unused outputs can be disabled
Output Features:
•
2 - 0.7V current mode differential output pairs (HCSL)
Block Diagram
OE0#
OE1#
DIF_0
SRC_IN
SRC_IN#
SPREAD
COMPATIBLE
PLL
DIF_1
PLL_BW
SMBDAT
SMBCLK
CONTROL
LOGIC
IREF
IDT
®
Two Output Differential Buffer for PCIe Gen3
1667C—04/20/11
1
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
