DATASHEET
56-pin CK505 for Intel Systems
Recommended Application:
56-pin CK505 compatible clock, w/fully integrated Vreg and series
resistors on differential outputs
Output Features:
•
2 - CPU differential low power push-pull pairs
•
7 - SRC differential push-pull pairs
•
1 - CPU/SRC selectable differential low power push-pull pair
•
1 - SRC/DOT selectable differential low power push-pull pair
•
1 - SRC/SE selectable differential push-pull pair/Single-ended
outputs
•
5 - PCI, 33MHz
•
1 - USB, 48MHz
•
1 - REF, 14.318MHz
Key Specifications:
•
CPU outputs cycle-cycle jitter < 85ps
•
SRC output cycle-cycle jitter < 125ps
•
PCI outputs cycle-cycle jitter < 250ps
•
+/- 100ppm frequency accuracy on all outputs
•
SRC outputs meet PCIe Gen2 when sourced from PLL3
Pin Configuration
PCI0/CR#_A 1
VDDPCI
PCI1/CR#_B
PCI2/TME
PCI3/CFG0
PCI4/SRC5_EN
PCI_F5/ITP_EN
GNDPCI
VDD48
USB_48MHz/FSLA
GND48
VDD96IO
DOTT_96_LRS/SRCT0_LRS
DOTC_96_LRS/SRCC0_LRS
GND
VDD
SRCT1_LRS/SE1
SRCC1_LRS/SE2
GND
VDDPLL3IO
SRCT2_LRS/SATAT_LRS
SRCC2_LRS/SATAC_LRS
GNDSRC
SRCT3_LRS/CR#_C
SRCC3_LRS/CR#_D
VDDSRCIO
SRCT4_LRS
SRCC4_LRS
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56 SCLK
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
SDATA
REF0/FSLC/TEST_SEL
VDDREF
X1
X2
GNDREF
FSLB/TEST_MODE
CK_PWRGD/PD#
VDDCPU
CPUT0_LRS
CPUC0_LRS
GNDCPU
CPUT1_F_LRS
CPUC1_F_LRS
VDDCPUIO
NC
CPUT2_ITP_LRS/SRCT8_LRS
CPUC2_ITP_LRS/SRCC8_LRS
VDDSRCIO
SRCT7_LRS/CR#_F
SRCC7_LRS/CR#_E
GNDSRC
SRCT6_LRS
SRCC6_LRS
VDDSRC
PCI_STOP#/SRCT5_LRS
CPU_STOP#/SRCC5_LRS
ICS9LPRS525
Features/Benefits:
•
Supports spread spectrum modulation, 0 to -0.5% down
spread
•
Supports CPU clks up to 400MHz
•
Uses external 14.318MHz crystal, external crystal load
caps are required for frequency tuning
Table 1: CPU Frequency Select Table
FS
L
C
B0b7
0
0
0
0
1
1
1
1
2
FS
L
B
B0b6
0
0
1
1
0
0
1
1
1
FS
L
A
B0b5
0
1
0
1
0
1
0
1
1
CPU
MHz
266.66
133.33
200.00
166.66
333.33
100.00
400.00
SRC
MHz
PCI
MHz
REF
MHz
USB DOT
MHz MHz
100.00
33.33 14.318 48.00 96.00
Reserved
1. FS
L
A and FS
L
B are low-threshold inputs.Please see V
IL_FS
and V
IH_FS
specifications in
the Input/Supply/Common Output Parameters Table for correct values.
Also refer to the Test Clarification Table.
2. FS
L
C is a three-level input. Please see the V
IL_FS
and V
IH_FS
specifications in the Input/Supply/Common Output Parameters Table for correct values.
56-SSOP & TSSOP
IDT
TM
PC MAIN CLOCK
9LPRS525
1484B—01/21/10
1
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
