IDT7132SA/LA and IDT 7142SA/LA
High Speed 2K x 8 Dual Port Static RAM
Military, Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature Supply Voltage Range
(5,6)
7132X20
(2)
7142X20
(2)
Com'l Only
Symbol
WRITE CYCLE
t
WC
t
EW
t
AW
t
AS
t
WP
t
WR
t
DW
t
HZ
t
DH
t
WZ
t
OW
Write Cycle Time
(3)
Chip Enable to End-of-Write
Address Valid to End-of-Write
Address Set-up Time
Write Pulse Width
(4)
Write Recovery Time
Data Valid to End-of-Write
Output High-Z Time
(1)
Data Hold Time
Write Enable to Output in High-Z
(1)
Output Active from End-of-Write
(1)
20
15
15
0
15
0
10
____
____
____
____
____
____
____
____
7132X25
(2)
7142X25
(2)
Com'l, Ind
& Military
Min.
Max.
7132X35
7142X35
Com'l &
Military
Min.
Max.
Unit
Parameter
Min.
Max.
25
20
20
0
15
0
12
____
____
____
____
____
____
____
____
35
30
30
0
25
0
15
____
____
____
____
____
____
____
____
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2692 tbl 09
10
____
10
____
15
____
0
____
0
____
0
____
10
____
10
____
15
____
0
0
0
7132X55
7142X55
Com'l &
Military
Symbol
WRITE CYCLE
t
WC
t
EW
t
AW
t
AS
t
WP
t
WR
t
DW
t
HZ
t
DH
t
WZ
t
OW
Write Cycle Time
(3)
Chip Enable to End-of-Write
Address Valid to End-of-Write
Address Set-up Time
Write Pulse Width
(4)
Write Recovery Time
Data Valid to End-of-Write
Output High-Z Time
(1)
Data Hold Time
Write Enable to Output in High-Z
(1)
Output Active from End-of-Write
(1)
55
40
40
0
30
0
20
____
____
____
____
____
____
____
____
7132X100
7142X100
Com'l &
Military
Min.
Max.
Unit
Parameter
Min.
Max.
100
90
90
0
55
0
40
____
____
____
____
____
____
____
____
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2692 tbl 10
25
____
40
____
0
____
0
____
30
____
40
____
0
0
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2). This parameter is guaranteed by device characterization
but is not production tested.
2. PLCC package only.
3. For Master/Slave combination, t
WC
= t
BAA
+ t
WP
, since R/W =
V
IL
must occur after t
BAA
.
4. If
OE
is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t
WP
or (t
WZ
+ t
DW
) to allow the I/O drivers to turn off data to be placed on the
bus for the required t
DW
. If
OE
is High during a R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t
WP
.
5. 'X' in part numbers indicates power rating (SA or LA).
6. Industrial temperature: for specific speeds, packages and powers contact your sales office.
9
6.42
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
