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IDT72211L15J PDF Datasheet浏览和下载

型号:
IDT72211L15J
PDF下载:
下载PDF文件 在线浏览文档
内容描述:
CMOS SyncFIFOO 64 ×9 , 256 ×9 , 512× 9 , 1024 X 9 , 2048 ×9和4096 ×9 [CMOS SyncFIFOO 64 X 9, 256 x 9, 512 x 9, 1024 X 9, 2048 X 9 and 4096 x 9]
文件大小:
155 K
文件页数:
14 Pages
品牌Logo:
品牌名称:
IDT [ INTEGRATED DEVICE TECHNOLOGY ]



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IDT72421/72201/72211/72221/72231/72241/72251 CMOS SyncFIFO™
64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(Commercial: V
CC
= 5V ± 10%, T
A
= 0°C to +70°C; Industrial: V
CC
= 5V ± 10%, T
A
= –40°C to +85°C)
Commercial
IDT72421L10
IDT72201L10
IDT72211L10
IDT72221L10
IDT72231L10
IDT72241L10
IDT72251L10
Min.
Max.
100
2
6.5
10
4.5
4.5
3
0.5
3
0.5
10
8
8
10
0
3
6
3
6
6.5
6.5
6.5
6.5
5
14
Com'l & Ind'l
(1)
IDT72421L15
IDT72201L15
IDT72211L15
IDT72221L15
IDT72231L15
IDT72241L15
IDT72251L15
Min.
Max.
66.7
2
10
15
6
6
4
1
4
1
15
10
10
15
0
3
8
3
8
10
10
10
10
6
15
Com'l & Ind'l
(1)
IDT72421L25
IDT72201L25
IDT72211L25
IDT72221L25
IDT72231L25
IDT72241L25
IDT72251L25
Min.
Max.
40
2
15
25
10
10
6
1
6
1
15
15
15
25
0
3
13
3
13
15
15
15
15
10
18
Symbol
f
S
t
A
t
CLK
t
CLKH
t
CLKL
t
DS
t
DH
t
ENS
t
ENH
t
RS
t
RSS
t
RSR
t
RSF
t
OLZ
t
OE
t
OHZ
t
WFF
t
REF
t
PAF
t
PAE
t
SKEW1
t
SKEW2
Parameter
Clock Cycle Frequency
Data Access Time
Clock Cycle Time
Clock High Time
Clock Low Time
Data Setup Time
Data Hold Time
Enable Setup Time
Enable Hold Time
Reset Pulse Width
(2)
Reset Setup Time
Reset Recovery Time
Reset to Flag and Output Time
Output Enable to Output in Low-Z
(3)
Output Enable to Output Valid
Output Enable to Output in High-Z
(3)
Write Clock to Full Flag
Read Clock to Empty Flag
Write Clock to Programmable Almost-Full Flag
Read Clock to Programmable Almost-Empty Flag
Skew time between Read Clock & Write Clock for
Empty Flag & Full Flag
Skew time between Read Clock & Write Clock for
Almost-Empty Flag & Programmable Almost-Full Flag
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES:
1. Industrial temperature range product for the 15ns and 25ns speed grades are available as standard product.
2. Pulse widths less than minimum values are not allowed.
3. Values guaranteed by design, not currently tested.
5V
AC TEST CONDITIONS
In Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
3ns
1.5V
1.5V
See Figure 1
1.1K
D.U.T.
680Ω
30pF*
CAPACITANCE
(Ta = +25°C, f = 1.0MHz)
Symbol
C
IN
(2)
C
OUT
(1,2)
Parameter
Input Capacitance
Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Max.
10
10
Unit
pF
pF
2655 drw 03
NOTES:
1. With output deselected (OE
V
IH
).
2. Characterized values, not currently tested.
or equivalent circuit
Figure 1. Output Load
*includes jig and scope capacitances
4