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IDT72211L15J PDF Datasheet浏览和下载

型号:
IDT72211L15J
PDF下载:
下载PDF文件 在线浏览文档
内容描述:
CMOS SyncFIFOO 64 ×9 , 256 ×9 , 512× 9 , 1024 X 9 , 2048 ×9和4096 ×9 [CMOS SyncFIFOO 64 X 9, 256 x 9, 512 x 9, 1024 X 9, 2048 X 9 and 4096 x 9]
文件大小:
155 K
文件页数:
14 Pages
品牌Logo:
品牌名称:
IDT [ INTEGRATED DEVICE TECHNOLOGY ]



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IDT72421/72201/72211/72221/72231/72241/72251 CMOS SyncFIFO™
64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9
t
RS
RS
t
RSS
REN1, REN2
t
RSS
WEN1
t
RSS
WEN2/LD
(1)
t
RSF
EF, PAE
t
RSF
FF, PAF
t
RSF
Q
0
- Q
8
t
RSR
t
RSR
t
RSR
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
OE
= 1
(2)
OE
= 0
2655 drw 06
NOTES:
1. Holding WEN2/LD HIGH during reset will make the pin act as a second write enable pin. Holding WEN2/LD LOW during reset will make the pin act as a load enable for the programmable
flag offset registers.
2. After reset, the outputs will be LOW if
OE
= 0 and tri-state if
OE
= 1.
3. The clocks (RCLK, WCLK) can be free-running during reset.
Figure 4. Reset Timing
t
CLK
t
CLKH
WCLK
t
DH
t
DS
D
0
- D
8
DATA IN VALID
t
ENS
WEN1
t
ENS
WEN2/
(If Applicable)
t
WFF
FF
t
SKEW1(1)
RCLK
REN1,
REN2
t
WFF
t
ENH
NO OPERATION
t
ENH
NO OPERATION
t
CLKL
2655 drw 07
NOTE:
1. t
SKEW1
is the minimum time between a rising RCLK edge and a rising WCLK edge for
FF
to change during the current clock cycle. If the time between the rising edge of RCLK
and the rising edge of WCLK is less than t
SKEW
1, then
FF
may not change state until the next WCLK edge.
Figure 5. Write Cycle Timing
8