IDT72421/72201/72211/72221/72231/72241/72251 CMOS SyncFIFO™
64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9
t
CLK
t
CLKH
RCLK
t
ENS
REN1,
REN2
t
REF
EF
t
A
Q
0
- Q
8
t
OLZ
t
OE
OE
WCLK
VALID DATA
t
OHZ
t
SKEW1
(1)
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
t
CLKL
t
ENH
NO OPERATION
t
REF
WEN1
WEN2
2655 drw 08
NOTE:
1. t
SKEW1
is the minimum time between a rising WCLK edge and a rising RCLK edge for
EF
to change during the current clock cycle. If the time between the rising edge of RCLK
and the rising edge of WCLK is less than t
SKEW1
, then
EF
may not change state until the next RCLK edge.
Figure 6. Read Cycle Timing
WCLK
t
DS
D
0
- D
8
t
ENS
WEN1
t
ENS
WEN2
(If Applicable)
t
SKEW1
RCLK
t
REF
EF
REN1,
REN2
t
ENS
t
FRL
(1)
D
1
D
0
(First Valid Write)
D
2
D
3
t
A
Q
0
- Q
8
t
OLZ
OE
NOTE:
1. When t
SKEW1
≥
minimum specification, t
FRL
= t
CLK
+ t
SKEW
1
When
t
SKEW1
<
minimum specification, t
FRL
= 2t
CLK
+ t
SKEW
1 or t
CLK
+ t
SKEW
1
The Latency Timings apply only at the Empty Boundary (EF = LOW).
t
A
D
0
D
1
t
OE
2655 drw 09
Figure 7. First Data Word Latency Timing
9
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
