2.5V, 3.3V ECL/LVPECL/LVDS DUAL
DIFFERENTIAL 2:1 MULTIPLEXER
The MC100ES6056 is a dual, fully differential 2:1 multiplexer. The differential data path
makes the device ideal for multiplexing low skew clock or other skew sensitive signals.
Multiple V
BB
pins are provided.
The V
BB
pin, an internally generated voltage supply, is available to this device only. For
single-ended input conditions, the unused differential input is connected to V
BB
as a
switching reference voltage. V
BB
may also rebias AC coupled inputs. When used,
decouple V
BB
and V
CC
via a 0.01
µF
capacitor and limit current sourcing or sinking to 0.5
mA. When not used, V
BB
should be left open.
The device features both individual and common select inputs to address both data
path and random logic applications.
The 100ES Series contains temperature compensation.
Features
•
•
•
•
•
•
•
•
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360 ps Typical Propagation Delays
Maximum Frequency > 3 GHz Typical
PECL Mode Operating Range: V
CC
= 2.375 V to 3.8 V with V
EE
= 0 V
ECL Mode Operating Range: V
CC
= 0 V with V
EE
= –2.375 V to –3.8 V
Open Input Default State
Separate and Common Select
Q Output Will Default LOW with Inputs Open or at V
EE
V
BB
Outputs
LVDS Input Compatible
20-Lead Pb-Free Package Available
MC100ES6056
DT SUFFIX
20-LEAD TSSOP PACKAGE
CASE 948E-03
EJ SUFFIX
20-LEAD TSSOP PACKAGE
Pb-FREE PACKAGE
CASE 948E-03
EG SUFFIX
20-LEAD SOIC PACKAGE
Pb-FREE PACKAGE
CASE 751D-07
ORDERING INFORMATION
Device
MC100ES6056DT
MC100ES6056DTR2
MC100ES6056EJ
MC100ES6056EJR2
MC100ES6056EG
MC100ES6056EGR2
Package
TSSOP-20
TSSOP-20
TSSOP-20 (Pb-Free)
TSSOP-20 (Pb-Free)
SOIC-20 (Pb-Free)
SOIC-20 (Pb-Free)
V
CC
20
Q0
19
Q0
18
SEL0 COM_SEL SEL1
17
16
15
V
CC
14
Q1
13
Q1
12
V
EE
11
1
0
1
0
1
D0a
2
D0a
3
V
BB0
4
D0b
5
D0b
6
D1a
7
D1a
8
V
BB1
9
D1b
10
D1b
Warning: All V
CC
and V
EE
pins must be externally connected to
Power Supply to guarantee proper operation.
Figure 1. 20-Lead Pinout
(Top View)
and Logic Diagram
IDT™ / ICS™
2:1 MULTIPLEXER
1
MC100ES6056 REV. 5 JULY 16, 2007
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
