IN1307
TWO-WIRE SERIAL DATA BUS
IN1307 supports the bi-directional two-wire bus and the protocol of the data exchange. The
bus can be controlled by the “master” device, which generates the cycle signal (SCL), controls ac-
cess to the bus, generates the statuses START and STOP. Typical configuration of the bus with
the two-wire protocol is indicated in Figure.
Data transfer can be initiated only when the bus is not occupied. In the process of the data
transfer the data line should remain stable, while the line of the cycle signal is in the high status.
Status alterations of the data line at that moment, when the cycle line is in the high status, will be
regarded as the control signals.
In compliance with this the following conditions are determined:
Bus not occupied: both the data line and the cycle signal are in the HIGH status.
Data transfer start: Status alteration of the data line during transition from HIGH to LOW,
while the cycle line is in the HIGH status, is determined as the status START.
Data transfer stop: Status alteration of the data line during transition from LOW to HIGH,
while the cycle line is in the HIGH status, is determined as the status STOP.
Valid data: Data line status complies with the valid data, when after the status START the
data line is stable during the HIGH status of the cycle signal. Data on the line should be altered at
the time of the LOW status of the cycle signal. One cycle pulse per one data bit.
Each data transfer starts at the beginning of the status START and ceases at the beginning
of the status STOP. Number of the data bytes, transferred between the statuses START and
STOP is not limited and is determined by the «master» device. Information is transferred byte by
byte, and each receipt is confirmed by the ninth byte. IN1307 operates in the normal mode only
(100 kHz).
Confirmation of receipt: Each receiving device, when it being addressed, has to generate
the recept confirmation after receiving each byte. «Master» device should generate the cycle
pulses, which are allocated in compliance with the confirmation bits.
If the receipt confirmation signal is in the high status, then on arrival of the confirmation cycle
pulse, the device, confirming the receipt, should switch over the SDA line to the low status. Of
course, there should be considered the pre-set time and the hold time. The «master» device
should signalize on completion of the data transfer to the “slave” device, ceasing generation of the
confirmation bit on receiving the receipt confirmation from the “slave” cycle pulse. In this case, the
«slave one should switch over the data line to the low status, in order to enable the «master» one
generate the condition of STOP.
2013, December, Ver.04
9
IKSEMICON [ IK SEMICON CO., LTD ]
