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IN74HC595AD 参数 Datasheet PDF下载

IN74HC595AD图片预览
型号: IN74HC595AD
PDF下载: 下载PDF文件 查看货源
内容描述: 8位串行输入/串行或并行输出移位锁存具有三态输出的高性能硅栅CMOS注册 [8-Bit Serial-Input/Serial or Parallel-Output Shift Register with Latched 3-State Outputs High-Performance Silicon-Gate CMOS]
分类和应用:
文件页数/大小: 10 页 / 200 K
品牌: IKSEMICON [ IK SEMICON CO., LTD ]
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IN74HC595A
AC ELECTRICAL CHARACTERISTICS (C
L
=50pF,Input t
r
=t
f
=6.0 ns)
V
CC
Symbol
Parameter
V
Guaranteed Limit
25
°C
to
-55°C
6.0
30
35
140
28
24
145
29
25
140
28
24
150
30
26
135
27
23
60
12
10
75
15
13
10
15
≤85
°C
4.8
24
28
175
35
30
180
36
31
175
35
30
190
38
33
170
34
29
75
15
13
95
19
16
10
15
≤125
°C
4.0
20
24
210
42
36
220
44
38
210
42
36
225
45
38
205
41
35
90
18
15
110
22
19
10
15
Unit
f
max
Minimum Clock Frequency (50% Duty Cycle)
(Figures 1and 7)
Maximum Propagation Delay, Shift Clock to SQ
H
(Figures 1and 7)
Maximum Propagation Delay , Reset to SQ
H
(Figures 2 and 7)
Maximum Propagation Delay , Latch Clock to
Q
A
-Q
H
(Figures 3 and 7)
Maximum Propagation Delay , Output Enable to
Q
A
-Q
H
(Figures 4 and 8)
Maximum Propagation Delay , Output Enable to
Q
A
-Q
H
(Figures 4 and 8)
Maximum Output Transition Time, Q
A
-Q
H
(Figures 3 and 7)
Maximum Output Transition Time, SQ
H
(Figures 1 and 7)
Maximum Input Capacitance
Maximum Three-State Output Capacitance
(Output in High-Impedance State), Q
A
-Q
H
Power Dissipation Capacitance (Per Package)
Used to determine the no-load dynamic power
consumption:
P
D
=C
PD
V
CC2
f+I
CC
V
CC
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
-
-
MHz
t
PLH
, t
PHL
ns
t
PHL
ns
t
PLH
, t
PHL
ns
t
PLZ
, t
PHZ
ns
t
PZL
, t
PZH
ns
t
TLH
, t
THL
ns
t
TLH
, t
THL
ns
C
IN
C
OUT
pF
pF
Typical @25°C,V
CC
=5.0 V
300
pF
C
PD
Rev. 00