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IN74HCT374ADW 参数 Datasheet PDF下载

IN74HCT374ADW图片预览
型号: IN74HCT374ADW
PDF下载: 下载PDF文件 查看货源
内容描述: 八路三态同相D触发器高性能硅栅CMOS [Octal 3-State Noninverting D Flip-Flop High-Performance Silicon-Gate CMOS]
分类和应用: 触发器
文件页数/大小: 6 页 / 303 K
品牌: IKSEMICON [ IK SEMICON CO., LTD ]
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IN74HCT374A
AC ELECTRICAL CHARACTERISTICS
(V
CC
=5.0 V
±
10%, C
L
=50pF,Input t
r
=t
f
=6.0 ns)
Guaranteed Limit
Symbol
Parameter
25
°C
to
-55°C
30
31
30
30
12
10
15
≤85°C
≤125°C
Unit
f
max
t
PLH
, t
PHL
t
PLZ
, t
PHZ
t
PZH
, t
PZL
t
TLH
, t
THL
C
IN
C
OUT
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 4)
Maximum Propagation Delay, Clock to Q
(Figures 1 and 4)
Maximum Propagation Delay, Output Enable to
Q (Figures 2 and 5)
Maximum Propagation Delay, Output Enable to
Q (Figures 2 and 5)
Maximum Output Transition Time, Any Output
(Figures 1 and 4)
Maximum Input Capacitance
Maximum Three-State Output Capacitance
(Output in High-Impedance State)
Power Dissipation Capacitance (Per Flip-Flop)
24
39
38
38
15
10
15
20
47
45
45
18
10
15
MHz
ns
ns
ns
ns
pF
pF
Typical @25°C,V
CC
=5.0 V
65
pF
C
PD
Used to determine the no-load dynamic power
consumption:
P
D
=C
PD
V
CC2
f+I
CC
V
CC
TIMING REQUIREMENTS
(V
CC
=5.0 V
±
10%, C
L
=50pF,Input t
r
=t
f
=6.0 ns)
Guaranteed Limit
Symbol
t
SU
t
h
t
w
t
r,
t
f
Parameter
Minimum Setup Time, Data to
Clock (Figure 3)
Minimum Hold Time, Clock
to Data (Figure 3)
Minimum Pulse Width, Clock
(Figure 1)
Maximum Input Rise and Fall
Times (Figure 1)
25
°C
to
-55°C
12
5.0
12
500
≤85°C
15
5.0
15
500
≤125°C
18
5.0
18
500
Unit
ns
ns
ns
ns
Rev. 00