欢迎访问ic37.com |
会员登录 免费注册
发布采购

ICE3BS03LJG 参数 Datasheet PDF下载

ICE3BS03LJG图片预览
型号: ICE3BS03LJG
PDF下载: 下载PDF文件 查看货源
内容描述: 离线式开关电源电流模式控制器,集成500V启动电池 [Off-Line SMPS Current Mode Controller with integrated 500V Startup Cell]
分类和应用: 电池开关控制器
文件页数/大小: 25 页 / 492 K
品牌: INFINEON [ INFINEON TECHNOLOGIES AG ]
 浏览型号ICE3BS03LJG的Datasheet PDF文件第5页浏览型号ICE3BS03LJG的Datasheet PDF文件第6页浏览型号ICE3BS03LJG的Datasheet PDF文件第7页浏览型号ICE3BS03LJG的Datasheet PDF文件第8页浏览型号ICE3BS03LJG的Datasheet PDF文件第10页浏览型号ICE3BS03LJG的Datasheet PDF文件第11页浏览型号ICE3BS03LJG的Datasheet PDF文件第12页浏览型号ICE3BS03LJG的Datasheet PDF文件第13页  
F3 PWM controller
ICE3BS03LJG
Functional Description
to the line variations. The current waveform slope will
change with the line variation, which controls the duty
cycle.
The external R
Sense
allows an individual adjustment of
the maximum source current of the external power
MOSFET.
To improve the Current Mode during light load
conditions the amplified current ramp of the PWM-OP
is superimposed on a voltage ramp, which is built by
the switch T2, the voltage source V1 and a resistor R1
(see Figure 6). Every time the oscillator shuts down for
maximum duty cycle limitation the switch T2 is closed
by V
OSC
. When the oscillator triggers the Gate Driver,
T2 is opened so that the voltage ramp can start.
In case of light load the amplified current ramp is too
small to ensure a stable regulation. In that case the
Voltage Ramp is a well defined signal for the
comparison with the FB-signal. The duty cycle is then
controlled by the slope of the Voltage Ramp.
By means of the time delay circuit which is triggered by
the inverted V
OSC
signal, the Gate Driver is switched-off
until it reaches approximately 156ns delay time (see
Figure 7). It allows the duty cycle to be reduced
continuously till 0% by decreasing V
FB
below that
threshold.
V
OSC
max.
Duty Cycle
Voltage Ramp
0.6V
FB
t
Gate Driver
156ns time delay
t
t
Soft-Start Comparator
PWM Comparator
FB
Oscillator
V
OSC
time delay
circuit (156ns)
Figure 7
Light Load Conditions
3.3.1
PWM-OP
C8
PWM-Latch
Gate Driver
10kΩ
T
2
C
1
Voltage Ramp
Figure 6
0.6V
X3.2
V
1
PWM OP
The input of the PWM-OP is applied over the internal
leading edge blanking to the external sense resistor
R
Sense
connected to pin CS. R
Sense
converts the source
current into a sense voltage. The sense voltage is
amplified with a gain of 3.2 by PWM OP. The output of
the PWM-OP is connected to the voltage source V
1
.
The voltage ramp with the superimposed amplified
current signal is fed into the positive inputs of the PWM-
Comparator C8 and the Soft-Start-Comparator (see
Figure 6).
3.3.2
PWM-Comparator
R
1
Improved Current Mode
The PWM-Comparator compares the sensed current
signal of the external power MOSFET with the
feedback signal V
FB
(see Figure 8). V
FB
is created by an
external optocoupler or external transistor in
combination with the internal pull-up resistor R
FB
and
provides the load information of the feedback circuitry.
When the amplified current signal of the external power
MOSFET exceeds the signal V
FB
the PWM-
Comparator switches off the Gate Driver.
Version 2.0
9
6 Dec 2007