IA186EM/IA188EM
Data Sheet
8-Bit/16-Bit Microcontrollers
February 25, 2011
LIST OF TABLES
Table 1. IA186EM TQFP Numeric Pin Listing............................................................................17
Table 2. IA186EM TQFP Alphabetic Pin Listing ........................................................................18
Table 3. IA188EM TQFP Numeric Pin Listing............................................................................20
Table 4. IA188EM TQFP Alphabetic Pin Listing ........................................................................21
Table 5. IA186EM PQFP Numeric Pin Listing............................................................................24
Table 6. IA186EM PQFP Alphabetic Pin Listing ........................................................................25
Table 7. IA188EM PQFP Numeric Pin Listing............................................................................27
Table 8. IA188EM PQFP Alphabetic Pin Listing ........................................................................28
Table 9. Bus Cycle Types for bhe_n and ad0 ...............................................................................31
Table 10. Bus Cycle Types for s2_n, s1_n, and s0_n...................................................................38
Table 11. IA186EM and IA188EM Absolute Maximum Ratings................................................42
Table 12. IA186EM and IA188EM Thermal Characteristics.......................................................42
Table 13. DC Characteristics Over Commercial Operating Ranges.............................................42
Table 14. Interrupt Types..............................................................................................................51
Table 15. Default Status of PIO Pins at Reset ..............................................................................56
Table 16. Peripheral Control Registers.........................................................................................58
Table 17. Peripheral Control Block Relocation Register..............................................................59
Table 18. Reset Configuration Register........................................................................................59
Table 19. Processor Release Level Register.................................................................................60
Table 20. Power-Save Control Register........................................................................................60
Table 21. Enable Dynamic RAM Refresh Control Register.........................................................61
Table 22. Count for Dynamic RAM Refresh Control Register ....................................................62
Table 23. Memory Partition for Dynamic RAM Refresh Control Register .................................62
Table 24. DMA Control Registers................................................................................................62
Table 25. DMA Transfer Count Registers....................................................................................64
Table 26. DMA Destination Address High Register ....................................................................65
Table 27. DMA Destination Address Low Register.....................................................................65
Table 28. DMA Source Address High Register............................................................................65
Table 29. DMA Source Address Low Register ............................................................................66
Table 30. MCS and PCS Auxiliary Register ................................................................................66
Table 31. Midrange Memory Chip Select Register ......................................................................68
Table 32. Peripheral Chip Select Register....................................................................................69
Table 33. Low-Memory Chip Select Register..............................................................................70
Table 34. Upper-Memory Chip Select Register ...........................................................................72
Table 35. Baud Rates ....................................................................................................................73
Table 36. Serial Port Baud Rate Divisor Registers.......................................................................73
Table 37. Serial Port Receive Data Register.................................................................................74
Table 38. Serial Port Transmit Data Register ...............................................................................74
Table 39. Serial Port Status Register ............................................................................................74
Table 40. Serial Port Control Register..........................................................................................75
Table 41. PIO Pin Assignments....................................................................................................77
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IA211050831-19
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