IA82510
Data Sheet
ASYNCHRONOUS SERIAL CONTROLLER
As of Production Ver. 01
AC Characteristics
Parameter
CLK period
CLK period
CLK Low Time
CLK High Time
Min
Max
Notes
Divide by Two
No Divide by
54 ns
54 ns
25 ns
25 ns
250 ns
108 ns
10 ns
10 ns
Divide by Two
Measured between 0.3 * VDD
and 0.7 * VDD
CLK Rise Time
Divide by Two
Measured between 0.3 * VDD
and 0.7 * VDD
CLK Fall Time
CLK Rise Time
15 ns
No Divide by
CLK Fall Time
15 ns
No Divide by
Crystal Frequency
Reset Width
RTS/DTR Low Setup
to Reset inactive
RTS/DTR Low Hold
after Reset inactive
1 Mhz
8 * Clock Period
6 * Clock Period
20 Mhz
Clock Period – 20 ns
2* clock period +
65 ns
7 ns
RDn Active Width
Address/CSn Setup
Time to RDn Active
Address/CSn Hold
after RDn Inactive
RDn or WRn Inactive
to Active Delay
0 ns
Clock Period +
15 ns
Data Out Float Delay
after RDn Inactive
40 ns
2 * Clock Period
+ 15 ns
7 ns
WRn Active Width
Address CSn Setup
Time to WRn Active
Address and CSn
hold Time after WRn
Data in Setup Time
to WRn Inactive
Data In Hold Time
after WRn Inactive
SCLK Period
0 ns
90 ns
12 ns
216 ns
3500 ns
250 ns
16x Clocking Mode
1x Clocking Mode
SCLK Period
RXD Setup Time to
SCLK High
RXD Hold Time after
SCLK High
250 ns
TXD Valid after SCLK
Low
TXD Delay after RXD
170 ns
170 ns
Remote Loopback
Copyright
innovASIC
2001
ENG211001219-01
www.innovasic.com
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