IA8044/IA8344
Data Sheet
SDLC Communications Controller
March 30, 2010
Table 41. Receive Field Length Register......................................................................................41
Table 42. Receive Control Byte Register .....................................................................................42
Table 43. DMA Count Register (DMA CNT)..............................................................................42
Table 44. DMA Count Register (FIFO)........................................................................................42
Table 45. SIU State Counter .........................................................................................................42
Table 46. Basic SDLC Frame .......................................................................................................44
Table 47. Frame Format Options..................................................................................................45
Table 48. External Program Memory Characteristics...................................................................50
Table 49. External Data Memory Characteristics.........................................................................50
Table 50. Serial Interface Characteristics .....................................................................................51
Table 51. External Clock Drive Characteristics ...........................................................................51
Table 52. Reset Values Register ...................................................................................................56
Table 53. Arithmetic Operations...................................................................................................57
Table 54. Logic Operations...........................................................................................................58
Table 55. Data Transfer ................................................................................................................59
Table 56. Boolean Manipulation...................................................................................................60
Table 57. Program Branches.........................................................................................................60
Table 58. Innovasic/Intel Part Number Cross-Reference for the PDIP........................................61
Table 59. Innovasic/Intel Part Number Cross-Reference for the PLCC.......................................61
Table 60. Summary of Errata........................................................................................................62
Table 61. Revision History ...........................................................................................................64
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